[PATCH] D118372: [SVE] Fix TypeSize->uint64_t implicit conversion in visitAlloca()

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin updated this revision to Diff 403955.
kmclaughlin marked 2 inline comments as done.
kmclaughlin edited the summary of this revision.
kmclaughlin added a comment.

- Fixed AllocSize to ensure we multiply by vscale for scalable vectors
- Added CHECK lines to the test in sve-alloca.ll


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118372/new/

https://reviews.llvm.org/D118372

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/test/CodeGen/AArch64/sve-alloca.ll


Index: llvm/test/CodeGen/AArch64/sve-alloca.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-alloca.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
+
+declare void @bar(<vscale x 4 x i64>*)
+
+define void @foo(<vscale x 4 x i64> %dst, i1 %cond) {
+; CHECK-LABEL: foo:
+; CHECK:         rdvl x9, #2
+; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    add x9, x9, #15
+; CHECK-NEXT:    and x9, x9, #0xfffffffffffffff0
+; CHECK-NEXT:    sub x8, x8, x9
+; CHECK-NEXT:    and x0, x8, #0xffffffffffffffe0
+; CHECK-NEXT:    mov sp, x0
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    st1d { z1.d }, p0, [x0, #1, mul vl]
+; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
+; CHECK-NEXT:    bl bar
+entry:
+  br i1 %cond, label %if.then, label %if.end
+
+if.then:
+  %ptr = alloca <vscale x 4 x i64>
+  store <vscale x 4 x i64> %dst, <vscale x 4 x i64>* %ptr
+  call void @bar(<vscale x 4 x i64>* %ptr)
+  br label %if.end
+
+if.end:
+  ret void
+}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4014,7 +4014,7 @@
   Type *Ty = I.getAllocatedType();
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   auto &DL = DAG.getDataLayout();
-  uint64_t TySize = DL.getTypeAllocSize(Ty);
+  TypeSize TySize = DL.getTypeAllocSize(Ty);
   MaybeAlign Alignment = std::max(DL.getPrefTypeAlign(Ty), I.getAlign());
 
   SDValue AllocSize = getValue(I.getArraySize());
@@ -4023,9 +4023,14 @@
   if (AllocSize.getValueType() != IntPtr)
     AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
 
-  AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
-                          AllocSize,
-                          DAG.getConstant(TySize, dl, IntPtr));
+  if (TySize.isScalable())
+    AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr, AllocSize,
+                            DAG.getVScale(dl, IntPtr,
+                                          APInt(IntPtr.getScalarSizeInBits(),
+                                                TySize.getKnownMinValue())));
+  else
+    AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr, AllocSize,
+                            DAG.getConstant(TySize, dl, IntPtr));
 
   // Handle alignment.  If the requested alignment is less than or equal to
   // the stack alignment, ignore it.  If the size is greater than or equal to


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