[PATCH] D116534: [RISCV] Set getMinVectorRegisterBitWidth to 16 if enable fixed length vector code gen for RVV

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

I think only VE and Aarch64 is meaningful for RISC-V as reference since we are the only 3 targets having scaleable vector support,  so I only take a look on those two targets:

VE: NO VLS code gen support, getMinVectorRegisterBitWidth always return 0.
AArch64: Return 64 as default, and set 128 for many core with this comment `// FIXME: remove this to enable 64-bit SLP if performance looks good.`[1]

My thought: This hook is describing capability of target, so I would prefer describe what we really can support, which is 2 x i8, I know there is concern about it having benefit or not, but I think that should be cost model stuffs, we could describe that on cost model in following patches, for example `2 x i8` and `(ST->getMinRVVVectorSizeInBits()) / 8 x i8` having same cost, so SLP and loop vectorization will using larger type if possible.

[1] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64Subtarget.cpp#L138


Repository:
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https://reviews.llvm.org/D116534