[PATCH] D112692: [RISCV] Generate pseudo instruction li

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

As the alias is _only_ matching addi with an X0 and a simm12 I don't think there's an real scenario where it would print a standalone li that would be reassembled to anything other than an addi.


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  https://reviews.llvm.org/D112692/new/

https://reviews.llvm.org/D112692