[PATCH] D110933: [RISCV] Add a test showing incorrect RVV stack alignment

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

I didn't understand the problem. In the second test case `rvv_stack_align16`, the sp will be udpated to sp -16 - vlenb x 2. It is aligned to 16 bytes for vlenb = 8, 16, ..., etc. Isn't it?
In addition, the memory alignment constraint is to align to the size of element. <vscale x 4 x i32> is to align 4, not align to 16.


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  https://reviews.llvm.org/D110933/new/

https://reviews.llvm.org/D110933