[llvm] 5188e2c - [x86] add AVX512 run for fcmp+logic ops; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 23 11:28:32 PDT 2021
Author: Sanjay Patel
Date: 2021-09-23T14:28:22-04:00
New Revision: 5188e2c9ce1fb33600270243bbc32b4b108f1019
URL: https://github.com/llvm/llvm-project/commit/5188e2c9ce1fb33600270243bbc32b4b108f1019
DIFF: https://github.com/llvm/llvm-project/commit/5188e2c9ce1fb33600270243bbc32b4b108f1019.diff
LOG: [x86] add AVX512 run for fcmp+logic ops; NFC
Suggested in D110342
Added:
Modified:
llvm/test/CodeGen/X86/fcmp-logic.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/fcmp-logic.ll b/llvm/test/CodeGen/X86/fcmp-logic.ll
index 80d0b2b2a87c..13584cdd3769 100644
--- a/llvm/test/CodeGen/X86/fcmp-logic.ll
+++ b/llvm/test/CodeGen/X86/fcmp-logic.ll
@@ -1,16 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-- -mattr=sse2 | FileCheck %s --check-prefixes=SSE
-; RUN: llc < %s -mtriple=x86_64-- -mattr=avx | FileCheck %s --check-prefixes=AVX
+; RUN: llc < %s -mtriple=x86_64-- -mattr=sse2 | FileCheck %s --check-prefixes=SSE2
+; RUN: llc < %s -mtriple=x86_64-- -mattr=avx | FileCheck %s --check-prefixes=AVX
+; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512f | FileCheck %s --check-prefixes=AVX
define i1 @olt_ole_and_f32(float %w, float %x, float %y, float %z) {
-; SSE-LABEL: olt_ole_and_f32:
-; SSE: # %bb.0:
-; SSE-NEXT: ucomiss %xmm0, %xmm1
-; SSE-NEXT: seta %cl
-; SSE-NEXT: ucomiss %xmm2, %xmm3
-; SSE-NEXT: setae %al
-; SSE-NEXT: andb %cl, %al
-; SSE-NEXT: retq
+; SSE2-LABEL: olt_ole_and_f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: ucomiss %xmm0, %xmm1
+; SSE2-NEXT: seta %cl
+; SSE2-NEXT: ucomiss %xmm2, %xmm3
+; SSE2-NEXT: setae %al
+; SSE2-NEXT: andb %cl, %al
+; SSE2-NEXT: retq
;
; AVX-LABEL: olt_ole_and_f32:
; AVX: # %bb.0:
@@ -27,16 +28,16 @@ define i1 @olt_ole_and_f32(float %w, float %x, float %y, float %z) {
}
define i1 @oge_oeq_or_f32(float %w, float %x, float %y, float %z) {
-; SSE-LABEL: oge_oeq_or_f32:
-; SSE: # %bb.0:
-; SSE-NEXT: ucomiss %xmm1, %xmm0
-; SSE-NEXT: setae %cl
-; SSE-NEXT: ucomiss %xmm3, %xmm2
-; SSE-NEXT: setnp %dl
-; SSE-NEXT: sete %al
-; SSE-NEXT: andb %dl, %al
-; SSE-NEXT: orb %cl, %al
-; SSE-NEXT: retq
+; SSE2-LABEL: oge_oeq_or_f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: ucomiss %xmm1, %xmm0
+; SSE2-NEXT: setae %cl
+; SSE2-NEXT: ucomiss %xmm3, %xmm2
+; SSE2-NEXT: setnp %dl
+; SSE2-NEXT: sete %al
+; SSE2-NEXT: andb %dl, %al
+; SSE2-NEXT: orb %cl, %al
+; SSE2-NEXT: retq
;
; AVX-LABEL: oge_oeq_or_f32:
; AVX: # %bb.0:
@@ -55,14 +56,14 @@ define i1 @oge_oeq_or_f32(float %w, float %x, float %y, float %z) {
}
define i1 @ord_one_xor_f32(float %w, float %x, float %y, float %z) {
-; SSE-LABEL: ord_one_xor_f32:
-; SSE: # %bb.0:
-; SSE-NEXT: ucomiss %xmm1, %xmm0
-; SSE-NEXT: setnp %cl
-; SSE-NEXT: ucomiss %xmm3, %xmm2
-; SSE-NEXT: setne %al
-; SSE-NEXT: xorb %cl, %al
-; SSE-NEXT: retq
+; SSE2-LABEL: ord_one_xor_f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: ucomiss %xmm1, %xmm0
+; SSE2-NEXT: setnp %cl
+; SSE2-NEXT: ucomiss %xmm3, %xmm2
+; SSE2-NEXT: setne %al
+; SSE2-NEXT: xorb %cl, %al
+; SSE2-NEXT: retq
;
; AVX-LABEL: ord_one_xor_f32:
; AVX: # %bb.0:
@@ -79,16 +80,16 @@ define i1 @ord_one_xor_f32(float %w, float %x, float %y, float %z) {
}
define i1 @une_ugt_and_f64(double %w, double %x, double %y, double %z) {
-; SSE-LABEL: une_ugt_and_f64:
-; SSE: # %bb.0:
-; SSE-NEXT: ucomisd %xmm1, %xmm0
-; SSE-NEXT: setp %al
-; SSE-NEXT: setne %cl
-; SSE-NEXT: orb %al, %cl
-; SSE-NEXT: ucomisd %xmm2, %xmm3
-; SSE-NEXT: setb %al
-; SSE-NEXT: andb %cl, %al
-; SSE-NEXT: retq
+; SSE2-LABEL: une_ugt_and_f64:
+; SSE2: # %bb.0:
+; SSE2-NEXT: ucomisd %xmm1, %xmm0
+; SSE2-NEXT: setp %al
+; SSE2-NEXT: setne %cl
+; SSE2-NEXT: orb %al, %cl
+; SSE2-NEXT: ucomisd %xmm2, %xmm3
+; SSE2-NEXT: setb %al
+; SSE2-NEXT: andb %cl, %al
+; SSE2-NEXT: retq
;
; AVX-LABEL: une_ugt_and_f64:
; AVX: # %bb.0:
@@ -107,14 +108,14 @@ define i1 @une_ugt_and_f64(double %w, double %x, double %y, double %z) {
}
define i1 @ult_uge_or_f64(double %w, double %x, double %y, double %z) {
-; SSE-LABEL: ult_uge_or_f64:
-; SSE: # %bb.0:
-; SSE-NEXT: ucomisd %xmm1, %xmm0
-; SSE-NEXT: setb %cl
-; SSE-NEXT: ucomisd %xmm2, %xmm3
-; SSE-NEXT: setbe %al
-; SSE-NEXT: orb %cl, %al
-; SSE-NEXT: retq
+; SSE2-LABEL: ult_uge_or_f64:
+; SSE2: # %bb.0:
+; SSE2-NEXT: ucomisd %xmm1, %xmm0
+; SSE2-NEXT: setb %cl
+; SSE2-NEXT: ucomisd %xmm2, %xmm3
+; SSE2-NEXT: setbe %al
+; SSE2-NEXT: orb %cl, %al
+; SSE2-NEXT: retq
;
; AVX-LABEL: ult_uge_or_f64:
; AVX: # %bb.0:
@@ -131,16 +132,16 @@ define i1 @ult_uge_or_f64(double %w, double %x, double %y, double %z) {
}
define i1 @une_uno_xor_f64(double %w, double %x, double %y, double %z) {
-; SSE-LABEL: une_uno_xor_f64:
-; SSE: # %bb.0:
-; SSE-NEXT: ucomisd %xmm1, %xmm0
-; SSE-NEXT: setp %al
-; SSE-NEXT: setne %cl
-; SSE-NEXT: orb %al, %cl
-; SSE-NEXT: ucomisd %xmm3, %xmm2
-; SSE-NEXT: setp %al
-; SSE-NEXT: xorb %cl, %al
-; SSE-NEXT: retq
+; SSE2-LABEL: une_uno_xor_f64:
+; SSE2: # %bb.0:
+; SSE2-NEXT: ucomisd %xmm1, %xmm0
+; SSE2-NEXT: setp %al
+; SSE2-NEXT: setne %cl
+; SSE2-NEXT: orb %al, %cl
+; SSE2-NEXT: ucomisd %xmm3, %xmm2
+; SSE2-NEXT: setp %al
+; SSE2-NEXT: xorb %cl, %al
+; SSE2-NEXT: retq
;
; AVX-LABEL: une_uno_xor_f64:
; AVX: # %bb.0:
@@ -159,14 +160,14 @@ define i1 @une_uno_xor_f64(double %w, double %x, double %y, double %z) {
}
define i1 @olt_olt_and_f32_f64(float %w, float %x, double %y, double %z) {
-; SSE-LABEL: olt_olt_and_f32_f64:
-; SSE: # %bb.0:
-; SSE-NEXT: ucomiss %xmm0, %xmm1
-; SSE-NEXT: seta %cl
-; SSE-NEXT: ucomisd %xmm2, %xmm3
-; SSE-NEXT: seta %al
-; SSE-NEXT: andb %cl, %al
-; SSE-NEXT: retq
+; SSE2-LABEL: olt_olt_and_f32_f64:
+; SSE2: # %bb.0:
+; SSE2-NEXT: ucomiss %xmm0, %xmm1
+; SSE2-NEXT: seta %cl
+; SSE2-NEXT: ucomisd %xmm2, %xmm3
+; SSE2-NEXT: seta %al
+; SSE2-NEXT: andb %cl, %al
+; SSE2-NEXT: retq
;
; AVX-LABEL: olt_olt_and_f32_f64:
; AVX: # %bb.0:
@@ -183,17 +184,17 @@ define i1 @olt_olt_and_f32_f64(float %w, float %x, double %y, double %z) {
}
define i1 @une_uno_xor_f64_use1(double %w, double %x, double %y, double %z, i1* %p) {
-; SSE-LABEL: une_uno_xor_f64_use1:
-; SSE: # %bb.0:
-; SSE-NEXT: ucomisd %xmm1, %xmm0
-; SSE-NEXT: setp %al
-; SSE-NEXT: setne %cl
-; SSE-NEXT: orb %al, %cl
-; SSE-NEXT: movb %cl, (%rdi)
-; SSE-NEXT: ucomisd %xmm3, %xmm2
-; SSE-NEXT: setp %al
-; SSE-NEXT: xorb %cl, %al
-; SSE-NEXT: retq
+; SSE2-LABEL: une_uno_xor_f64_use1:
+; SSE2: # %bb.0:
+; SSE2-NEXT: ucomisd %xmm1, %xmm0
+; SSE2-NEXT: setp %al
+; SSE2-NEXT: setne %cl
+; SSE2-NEXT: orb %al, %cl
+; SSE2-NEXT: movb %cl, (%rdi)
+; SSE2-NEXT: ucomisd %xmm3, %xmm2
+; SSE2-NEXT: setp %al
+; SSE2-NEXT: xorb %cl, %al
+; SSE2-NEXT: retq
;
; AVX-LABEL: une_uno_xor_f64_use1:
; AVX: # %bb.0:
@@ -214,17 +215,17 @@ define i1 @une_uno_xor_f64_use1(double %w, double %x, double %y, double %z, i1*
}
define i1 @une_uno_xor_f64_use2(double %w, double %x, double %y, double %z, i1* %p) {
-; SSE-LABEL: une_uno_xor_f64_use2:
-; SSE: # %bb.0:
-; SSE-NEXT: ucomisd %xmm1, %xmm0
-; SSE-NEXT: setp %al
-; SSE-NEXT: setne %cl
-; SSE-NEXT: orb %al, %cl
-; SSE-NEXT: ucomisd %xmm3, %xmm2
-; SSE-NEXT: setp %al
-; SSE-NEXT: setp (%rdi)
-; SSE-NEXT: xorb %cl, %al
-; SSE-NEXT: retq
+; SSE2-LABEL: une_uno_xor_f64_use2:
+; SSE2: # %bb.0:
+; SSE2-NEXT: ucomisd %xmm1, %xmm0
+; SSE2-NEXT: setp %al
+; SSE2-NEXT: setne %cl
+; SSE2-NEXT: orb %al, %cl
+; SSE2-NEXT: ucomisd %xmm3, %xmm2
+; SSE2-NEXT: setp %al
+; SSE2-NEXT: setp (%rdi)
+; SSE2-NEXT: xorb %cl, %al
+; SSE2-NEXT: retq
;
; AVX-LABEL: une_uno_xor_f64_use2:
; AVX: # %bb.0:
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