[PATCH] D109300: [AMDGPU] Make vector superclasses allocatable

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

Yet another question concerns gfx90a. Assume we are reading matrix C from memory into a register tuple. The mfma would need to use AGPR, but the load may use either AGPR or VGPR and has AV operand (same for a store). How likely will it happen that a VGPR tuple will be used for the load and then copied into AGPR? Can this happen?


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https://reviews.llvm.org/D109300