[PATCH] D109379: Implementation of PPC lowering for vp_load/vp_store with no mask

Fri Sep 10 02:45:45 PDT 2021

nemanjai added inline comments.

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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:2437

+def SDTVPLoad: SDTypeProfile<1, 4, [
+  SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisSameNumEltsAs<0, 3>, SDTCisInt<3>, SDTCisInt<4>
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Why are these here? These nodes are target independent so it definitely seems like the wrong thing to do to define them in a PPC-specific file.

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Comment at: llvm/test/CodeGen/PowerPC/ldst-with-length-vector.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
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This needs to have a big endian line as well and also a `-O0` for each to ensure that it works with FastISEL.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109379/new/

https://reviews.llvm.org/D109379