[PATCH] D108598: [ARC] Add codegen for the readcyclecounter intrinsic along with disassembly for associated instructions

[Thomas Johnson via Phabricator via llvm-commits]

thomasjohns created this revision.
thomasjohns added a reviewer: marksl.
Herald added a subscriber: hiraditya.
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Herald added a project: LLVM.

This adds lowering rules for the `llvm.readcyclecounter` intrinsic along with a codegen test for the ARC backend. To perform the lowering, we needed to generate the LR (Load from Auxiliary Register) instruction to read from the `COUNT0` timer register (which has number 33 or 0x22). Thus, this patch also adds support for the LR instruction with both LR_rs12 and LR_ru6 immediate formats along with custom disassembler code and tests.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108598

Files:
  llvm/lib/Target/ARC/ARCISelLowering.cpp
  llvm/lib/Target/ARC/ARCISelLowering.h
  llvm/lib/Target/ARC/ARCInstrFormats.td
  llvm/lib/Target/ARC/ARCInstrInfo.td
  llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp
  llvm/test/CodeGen/ARC/intrinsics.ll
  llvm/test/MC/Disassembler/ARC/ldst.txt

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