[PATCH] D107658: [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

What's the reasoning behind the current set of opcodes? E.g. are there cases where div[u]w/rem[u]w or sra[i]w/srl[i]w are worth using?



================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h:61
 
+  bool hasAllNBitUsers(SDNode *N, unsigned Bits) const;
+  bool hasAllWUsers(SDNode *N) const { return hasAllNBitUsers(N, 32); }
----------------
NBit with N being the SDNode is slightly confusing at first glance, though obvious once you stop and think. Unfortunate collision.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1258
+def addw : PatFrag<(ops node:$lhs, node:$rhs),
+                   (add node:$lhs, node:$rhs), [{
+  return hasAllWUsers(Node);
----------------
You could have a class for this so you just `def addw : PatFragFoo<add>;` etc and avoid the repetition


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1299
 
+// Select W instructions without sext_inreg if only the lower 32-bits of the
+// result are used.
----------------
Nit: 32-bit but 32 bits


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1301
+// result are used.
+def : Pat<(addw GPR:$rs1, GPR:$rs2), (ADDW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(addw GPR:$rs1, simm12:$imm12), (ADDIW GPR:$rs1, simm12:$imm12)>;
----------------
PatGprGpr/PatGprSimm12?


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