[PATCH] D105130: [RISCV] Enable interleaved access vectorization

Thu Jul 29 08:05:41 PDT 2021

luke957 added a comment.

In D105130#2909219 <https://reviews.llvm.org/D105130#2909219>, @craig.topper wrote:

> In D105130#2902226 <https://reviews.llvm.org/D105130#2902226>, @luke957 wrote:
>
>> In D105130#2847617 <https://reviews.llvm.org/D105130#2847617>, @craig.topper wrote:
>>
>>> Please upload patches with full context using -U999999 has documented here https://releases.llvm.org/11.0.0/docs/Phabricator.html#requesting-a-review-via-the-web-interface
>>>
>>> Do you plan to map these to segment load/store instructions in the future?
>>
>> Yeah, segment load/store instructions are naturally suitable for mapping these. Do we need to create a new RISCVISD?
>
> I believe we need to run the InterleavedAccessPass and and and implement TargetLowering::LowerInterleavedLoad/Store to create IR intrinsics. That's how it is done on ARM for their vldX and vstX intstructions.

Yeah, I think that is the right direction. Thanks. It seems I should submit a patch implementing TargetLowering::LowerInterleavedLoad/Store before this one.

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https://reviews.llvm.org/D105130