[PATCH] D106601: [RISCV] Teach vsetvli insertion pass that it doesn't need to insert vsetvli for unit-stride or strided loads/stores in some cases.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D106601#2909717 <https://reviews.llvm.org/D106601#2909717>, @rogfer01 wrote:

> I'm curious: why can't we apply a similar approach to loads as well? Don't they compute the EEW and EMUL in a similar way?

I initially didn't do it because I figured in most cases you'd still end up with a vsetvli after the load anyway. But there do seem to be some improvements in the test changes so I've added it.

> Also I think this could be applied to non-unit stride. I understand indexed memory accesses are the odd ones here.

You're right. I've added those now. I think we could also do segment load/stores, but I think the switch statement would become even more ridiculous and we should move to TSFlags. So I'd like to look at that as a follow up.

>   vsetivli zero, 2, e32, mf2, ta, mu
>   vle32.v v25, (a0)
>   vfwcvt.rtz.xu.f.v v26, v25
>   vsetvli zero, zero, e64, m1, ta, mu
>   # the previous vsetvli can be removed because
>   # a vle64 under SEW=32 and LMUL=1/2
>   # will be executed as
>   # EEW=64
>   # EMUL=(EEW/SEW) * LMUL=(64/32)*(1/2)=1
>   vle64.v v26, (a1) 




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106601/new/

https://reviews.llvm.org/D106601