[PATCH] D106237: [ISel] Port AArch64 HADD and RHADD to ISel

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: RKSimon, spatel, efriedma, craig.topper.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
dmgreen requested review of this revision.
Herald added a project: LLVM.

This ports the aarch64 combines for HADD and RHADD over to DAG combine, so that they can be used in more architectures (notably MVE in a followup patch).  The code was rewritten in the process to detect `shr(add(ext(A), ext(B)), 1)` and produce `ext(hadd(A, B))` as opposed to the original detecting starting from a `trunc(shr(...))`.

The general pattern for a HADDS is

  %xe = sext i8 %x to i32
  %ye = sext i8 %y to i32
  %a = add i32 %xe, %ye
  %r = ashr i32 %a, 1
  %t = trunc i32 %r to i8

A HADDU is equivalent with lshr and zext.  A RHADD also includes an extra round, so includes an extra add of 1.

For signed values, because only the bottom bits are demanded llvm will transform the above to use a lshr too, as opposed to ashr. In order to correctly detect the hadd we need to know the demanded bits to turn it back.


https://reviews.llvm.org/D106237

Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/arm64-vhadd.ll

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