[PATCH] D103898: [VP] Vector predicated vector splice intrinsic

[Vineet Kumar via Phabricator via llvm-commits]

vkmr added a comment.

In D103898#2809074 <https://reviews.llvm.org/D103898#2809074>, @craig.topper wrote:

> Are evl1 and evl2 likely to be the same value? Do you have an example when they would be different?

For a first order reduction, using a tail-folded loop with VP, if the EVL is computed using target-specific instructions, there is no guarantee that the EVL for the previous iteration would be the same as the EVL for current iteration or even that it would be equal to the runtime VF. For a more specific example, for RISC-V, the constraints on the `vset{i}vl{i}` instruction allow the EVL for the last non-tail iteration to be less than the runtime VF and unequal to the EVL for the tail iteration.


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