[PATCH] D103629: [AArch64] Cost-model i8 vector loads/stores

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added a comment.

In D103629#2799380 <https://reviews.llvm.org/D103629#2799380>, @efriedma wrote:

> The two-instruction sequence leaves the bits in the right positions for a `<4 x i16>`.  If you need a `<4 x i32>`, you need another zip.  If you need sign-extension, you need to sshr the result or something like that.  So "%x = load <4 x i8>, <4 x i8>* %a  %y = sext <4 x i8> %x to <4 x i32>" would be four instructions total.

Ah, thanks, makes sense! I was stuck with the idea that this would just require 2 instructions (for an example like this), which I didn't get.


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