[PATCH] D98232: [regalloc] Ensure Query::collectInterferringVregs is called before interval iteration

[Nikita Popov via Phabricator via llvm-commits]

nikic accepted this revision.
nikic added a comment.
This revision is now accepted and ready to land.

The proposed approach is fine from my side at least. Flipping the switch for AArch64 as well would be good.



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Comment at: llvm/lib/CodeGen/RegAllocGreedy.cpp:1063
                                  SmallVectorImpl<Register> &NewVRegs) {
-  // Make sure that VirtReg has a cascade number, and assign that cascade
+  // Make sure th5at VirtReg has a cascade number, and assign that cascade
   // number to every evicted register. These live ranges than then only be
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nit: A 5 snuck in.


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Comment at: llvm/test/CodeGen/X86/i128-mul.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86-NOBMI
+; RUN: llc -consider-local-interval-cost < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86-NOBMI
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+bmi2 | FileCheck %s --check-prefix=X86-BMI
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Don't think regalloc details are important for this test and the two below. Might want to regenerate the output rather than adding the flag for these. (The two tests above specifically test for regalloc behavior.)


Repository:
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https://reviews.llvm.org/D98232