[PATCH] D97646: [ASan][RISCV] Fix RISC-V memory mapping

Luís Marques via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Mar 17 08:14:55 PDT 2021


luismarques added a comment.

In D97646#2607526 <https://reviews.llvm.org/D97646#2607526>, @vitalybuka wrote:

> LGTM, but better if someone with RISCV experience checks this too

I would certainly appreciate such feedback, but perhaps this should be committed now/soon. Here's why I think so:

- In personal correspondence with @EccoTheDolphin I had confirmed that the current mapping RISC-V mapping needed cleaning/fixing, and that the current values had been adjusted to deal with a specific test system situation that isn't representative.
- Two weeks ago in the RISC-V community sync-up call we also brought attention to this patch. It seems less likely now that additional feedback will be provided.
- We know that some things are broken without this patch. With it, we're currently not aware of any issue or reason to believe it's incorrect.
- We can always further improve on this patch later if it still isn't quite correct.

@EccoTheDolphin Are you able to review this in the near/medium term?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97646/new/

https://reviews.llvm.org/D97646



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