[llvm] a968e7b - [ARM] KnownBits for CSINC/CSNEG/CSINV
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 4 00:40:34 PST 2021
Author: David Green
Date: 2021-03-04T08:40:20Z
New Revision: a968e7b82eac364d411c81aae58722a0b3a4b29c
URL: https://github.com/llvm/llvm-project/commit/a968e7b82eac364d411c81aae58722a0b3a4b29c
DIFF: https://github.com/llvm/llvm-project/commit/a968e7b82eac364d411c81aae58722a0b3a4b29c.diff
LOG: [ARM] KnownBits for CSINC/CSNEG/CSINV
This adds some simple known bits handling for the three CSINC/NEG/INV
instructions. From the operands known bits we can compute the common
bits of the first operand and incremented/negated/inverted second
operand. The first, especially CSINC ZR, ZR, comes up fair amount in the
tests. The others are more rare so a unit test for them is added.
Differential Revision: https://reviews.llvm.org/D97788
Added:
llvm/unittests/Target/ARM/ARMSelectionDAGTest.cpp
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
llvm/test/CodeGen/Thumb2/active_lane_mask.ll
llvm/test/CodeGen/Thumb2/mve-ctlz.ll
llvm/test/CodeGen/Thumb2/mve-cttz.ll
llvm/test/CodeGen/Thumb2/mve-fmas.ll
llvm/test/CodeGen/Thumb2/mve-fmath.ll
llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
llvm/test/CodeGen/Thumb2/mve-masked-store.ll
llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll
llvm/test/CodeGen/Thumb2/mve-pred-and.ll
llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
llvm/test/CodeGen/Thumb2/mve-pred-not.ll
llvm/test/CodeGen/Thumb2/mve-pred-or.ll
llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
llvm/test/CodeGen/Thumb2/mve-selectcc.ll
llvm/test/CodeGen/Thumb2/mve-vcmp.ll
llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
llvm/unittests/Target/ARM/CMakeLists.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 731d76f3c4c6..48a499ee39fc 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -17800,6 +17800,28 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
Known = KnownOp.zext(32);
break;
}
+ case ARMISD::CSINC:
+ case ARMISD::CSINV:
+ case ARMISD::CSNEG: {
+ KnownBits KnownOp0 = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
+ KnownBits KnownOp1 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
+
+ // The result is either:
+ // CSINC: KnownOp0 or KnownOp1 + 1
+ // CSINV: KnownOp0 or ~KnownOp1
+ // CSNEG: KnownOp0 or KnownOp1 * -1
+ if (Op.getOpcode() == ARMISD::CSINC)
+ KnownOp1 = KnownBits::computeForAddSub(
+ true, false, KnownOp1, KnownBits::makeConstant(APInt(32, 1)));
+ else if (Op.getOpcode() == ARMISD::CSINV)
+ std::swap(KnownOp1.Zero, KnownOp1.One);
+ else if (Op.getOpcode() == ARMISD::CSNEG)
+ KnownOp1 = KnownBits::computeForMul(
+ KnownOp1, KnownBits::makeConstant(APInt(32, -1)));
+
+ Known = KnownBits::commonBits(KnownOp0, KnownOp1);
+ break;
+ }
}
}
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
index 303c00170b51..c9df1bb2e2eb 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
@@ -19,11 +19,9 @@ define arm_aapcs_vfpcc void @fast_float_mul(float* nocapture %a, float* nocaptur
; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: cmp r5, r0
; CHECK-NEXT: cset r5, hi
-; CHECK-NEXT: ands r4, r5
-; CHECK-NEXT: lsls r4, r4, #31
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: andeq.w r5, lr, r12
-; CHECK-NEXT: lslseq.w r5, r5, #31
+; CHECK-NEXT: tst r5, r4
+; CHECK-NEXT: it eq
+; CHECK-NEXT: andseq.w r5, lr, r12
; CHECK-NEXT: beq .LBB0_4
; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
; CHECK-NEXT: subs r5, r3, #1
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
index d143976927b2..b79d33e55bb2 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
@@ -26,11 +26,9 @@ define arm_aapcs_vfpcc void @float_float_mul(float* nocapture readonly %a, float
; CHECK-NEXT: cmp r4, r2
; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: mov.w r12, #0
-; CHECK-NEXT: ands r5, r4
-; CHECK-NEXT: lsls r5, r5, #31
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: andeq r7, r6
-; CHECK-NEXT: lslseq.w r7, r7, #31
+; CHECK-NEXT: tst r4, r5
+; CHECK-NEXT: it eq
+; CHECK-NEXT: andseq.w r7, r7, r6
; CHECK-NEXT: beq .LBB0_11
; CHECK-NEXT: .LBB0_4: @ %for.body.preheader22
; CHECK-NEXT: mvn.w r7, r12
@@ -241,11 +239,9 @@ define arm_aapcs_vfpcc void @float_float_add(float* nocapture readonly %a, float
; CHECK-NEXT: cmp r4, r2
; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: mov.w r12, #0
-; CHECK-NEXT: ands r5, r4
-; CHECK-NEXT: lsls r5, r5, #31
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: andeq r7, r6
-; CHECK-NEXT: lslseq.w r7, r7, #31
+; CHECK-NEXT: tst r4, r5
+; CHECK-NEXT: it eq
+; CHECK-NEXT: andseq.w r7, r7, r6
; CHECK-NEXT: beq .LBB1_11
; CHECK-NEXT: .LBB1_4: @ %for.body.preheader22
; CHECK-NEXT: mvn.w r7, r12
@@ -456,11 +452,9 @@ define arm_aapcs_vfpcc void @float_float_sub(float* nocapture readonly %a, float
; CHECK-NEXT: cmp r4, r2
; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: mov.w r12, #0
-; CHECK-NEXT: ands r5, r4
-; CHECK-NEXT: lsls r5, r5, #31
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: andeq r7, r6
-; CHECK-NEXT: lslseq.w r7, r7, #31
+; CHECK-NEXT: tst r4, r5
+; CHECK-NEXT: it eq
+; CHECK-NEXT: andseq.w r7, r7, r6
; CHECK-NEXT: beq .LBB2_11
; CHECK-NEXT: .LBB2_4: @ %for.body.preheader22
; CHECK-NEXT: mvn.w r7, r12
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
index 41cfce6aa2bf..f70a5da8a0cc 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
@@ -393,11 +393,9 @@ define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_char(i8* nocapture readonly
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: cmp r4, r3
; CHECK-NEXT: cset r4, hi
-; CHECK-NEXT: ands r5, r4
-; CHECK-NEXT: lsls r5, r5, #31
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: andeq r7, r6
-; CHECK-NEXT: lslseq.w r7, r7, #31
+; CHECK-NEXT: tst r4, r5
+; CHECK-NEXT: it eq
+; CHECK-NEXT: andseq.w r7, r7, r6
; CHECK-NEXT: beq .LBB5_4
; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
; CHECK-NEXT: sub.w r4, r12, #1
@@ -691,11 +689,9 @@ define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_uchar(i8* nocapture readonl
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: cmp r4, r3
; CHECK-NEXT: cset r4, hi
-; CHECK-NEXT: ands r5, r4
-; CHECK-NEXT: lsls r5, r5, #31
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: andeq r7, r6
-; CHECK-NEXT: lslseq.w r7, r7, #31
+; CHECK-NEXT: tst r4, r5
+; CHECK-NEXT: it eq
+; CHECK-NEXT: andseq.w r7, r7, r6
; CHECK-NEXT: beq .LBB7_4
; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
; CHECK-NEXT: sub.w r4, r12, #1
@@ -989,11 +985,9 @@ define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_int(i32* nocapture readonly
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: cmp r4, r3
; CHECK-NEXT: cset r4, hi
-; CHECK-NEXT: ands r5, r4
-; CHECK-NEXT: lsls r5, r5, #31
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: andeq r7, r6
-; CHECK-NEXT: lslseq.w r7, r7, #31
+; CHECK-NEXT: tst r4, r5
+; CHECK-NEXT: it eq
+; CHECK-NEXT: andseq.w r7, r7, r6
; CHECK-NEXT: beq .LBB9_4
; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
; CHECK-NEXT: sub.w r4, r12, #1
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
index c8c057c048d8..3f8ec51ca84c 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
@@ -661,7 +661,7 @@ define i32 @wrongop(%struct.date* nocapture readonly %pd) {
; CHECK-NEXT: movw r3, :lower16:days
; CHECK-NEXT: movs r4, #52
; CHECK-NEXT: movt r3, :upper16:days
-; CHECK-NEXT: mla r1, r1, r4, r3
+; CHECK-NEXT: smlabb r1, r1, r4, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: vmov.32 q0[0], r0
diff --git a/llvm/test/CodeGen/Thumb2/active_lane_mask.ll b/llvm/test/CodeGen/Thumb2/active_lane_mask.ll
index 651ed43ec14e..91a9133d8eb8 100644
--- a/llvm/test/CodeGen/Thumb2/active_lane_mask.ll
+++ b/llvm/test/CodeGen/Thumb2/active_lane_mask.ll
@@ -464,11 +464,11 @@ define void @test_width2(i32* nocapture readnone %x, i32* nocapture %y, i8 zeroe
; CHECK-NEXT: eor.w r0, r5, r3
; CHECK-NEXT: orrs.w r0, r0, r12
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: teq.w r7, r9
; CHECK-NEXT: cset r2, ne
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov q4[2], q4[0], r2, r0
; CHECK-NEXT: vmov q4[3], q4[1], r2, r0
diff --git a/llvm/test/CodeGen/Thumb2/mve-ctlz.ll b/llvm/test/CodeGen/Thumb2/mve-ctlz.ll
index 9750b888804c..5fe47320c7b0 100644
--- a/llvm/test/CodeGen/Thumb2/mve-ctlz.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-ctlz.ll
@@ -4,26 +4,26 @@
define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){
; CHECK-LABEL: ctlz_2i64_0_t:
; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov r0, s3
+; CHECK-NEXT: clz r2, r2
; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: add.w r2, r2, #32
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: lsls r1, r1, #31
-; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: clz r1, r1
-; CHECK-NEXT: add.w r1, r1, #32
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
-; CHECK-NEXT: clzne r1, r0
+; CHECK-NEXT: clzne r2, r0
+; CHECK-NEXT: vmov s6, r2
+; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov r0, s1
-; CHECK-NEXT: vmov s6, r1
+; CHECK-NEXT: clz r2, r2
; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: add.w r2, r2, #32
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: lsls r1, r1, #31
-; CHECK-NEXT: vmov r1, s0
-; CHECK-NEXT: clz r1, r1
-; CHECK-NEXT: add.w r1, r1, #32
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
-; CHECK-NEXT: clzne r1, r0
-; CHECK-NEXT: vmov s4, r1
+; CHECK-NEXT: clzne r2, r0
+; CHECK-NEXT: vmov s4, r2
; CHECK-NEXT: vldr s5, .LCPI0_0
; CHECK-NEXT: vmov.f32 s7, s5
; CHECK-NEXT: vmov q0, q1
@@ -70,26 +70,26 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_1_t(<2 x i64> %src){
; CHECK-LABEL: ctlz_2i64_1_t:
; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov r0, s3
+; CHECK-NEXT: clz r2, r2
; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: add.w r2, r2, #32
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: lsls r1, r1, #31
-; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: clz r1, r1
-; CHECK-NEXT: add.w r1, r1, #32
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
-; CHECK-NEXT: clzne r1, r0
+; CHECK-NEXT: clzne r2, r0
+; CHECK-NEXT: vmov s6, r2
+; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov r0, s1
-; CHECK-NEXT: vmov s6, r1
+; CHECK-NEXT: clz r2, r2
; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: add.w r2, r2, #32
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: lsls r1, r1, #31
-; CHECK-NEXT: vmov r1, s0
-; CHECK-NEXT: clz r1, r1
-; CHECK-NEXT: add.w r1, r1, #32
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
-; CHECK-NEXT: clzne r1, r0
-; CHECK-NEXT: vmov s4, r1
+; CHECK-NEXT: clzne r2, r0
+; CHECK-NEXT: vmov s4, r2
; CHECK-NEXT: vldr s5, .LCPI4_0
; CHECK-NEXT: vmov.f32 s7, s5
; CHECK-NEXT: vmov q0, q1
diff --git a/llvm/test/CodeGen/Thumb2/mve-cttz.ll b/llvm/test/CodeGen/Thumb2/mve-cttz.ll
index e17107cf66cf..73103f2843ea 100644
--- a/llvm/test/CodeGen/Thumb2/mve-cttz.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-cttz.ll
@@ -4,33 +4,33 @@
define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_0_t(<2 x i64> %src){
; CHECK-LABEL: cttz_2i64_0_t:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov r0, s2
+; CHECK-NEXT: vmov q1, q0
+; CHECK-NEXT: vmov r2, s7
+; CHECK-NEXT: vmov r0, s6
+; CHECK-NEXT: rbit r2, r2
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: rbit r0, r0
+; CHECK-NEXT: clz r2, r2
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: lsls r1, r1, #31
-; CHECK-NEXT: vmov r1, s3
-; CHECK-NEXT: rbit r1, r1
-; CHECK-NEXT: clz r1, r1
-; CHECK-NEXT: add.w r1, r1, #32
+; CHECK-NEXT: adds r2, #32
+; CHECK-NEXT: rbit r0, r0
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
-; CHECK-NEXT: clzne r1, r0
-; CHECK-NEXT: vmov r0, s0
-; CHECK-NEXT: vmov s6, r1
+; CHECK-NEXT: clzne r2, r0
+; CHECK-NEXT: vmov s2, r2
+; CHECK-NEXT: vmov r2, s5
+; CHECK-NEXT: vmov r0, s4
+; CHECK-NEXT: rbit r2, r2
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: rbit r0, r0
+; CHECK-NEXT: clz r2, r2
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: lsls r1, r1, #31
-; CHECK-NEXT: vmov r1, s1
-; CHECK-NEXT: rbit r1, r1
-; CHECK-NEXT: clz r1, r1
-; CHECK-NEXT: add.w r1, r1, #32
+; CHECK-NEXT: adds r2, #32
+; CHECK-NEXT: rbit r0, r0
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
-; CHECK-NEXT: clzne r1, r0
-; CHECK-NEXT: vmov s4, r1
-; CHECK-NEXT: vldr s5, .LCPI0_0
-; CHECK-NEXT: vmov.f32 s7, s5
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: clzne r2, r0
+; CHECK-NEXT: vmov s0, r2
+; CHECK-NEXT: vldr s1, .LCPI0_0
+; CHECK-NEXT: vmov.f32 s3, s1
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
@@ -80,33 +80,33 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_1_t(<2 x i64> %src){
; CHECK-LABEL: cttz_2i64_1_t:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov r0, s2
+; CHECK-NEXT: vmov q1, q0
+; CHECK-NEXT: vmov r2, s7
+; CHECK-NEXT: vmov r0, s6
+; CHECK-NEXT: rbit r2, r2
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: rbit r0, r0
+; CHECK-NEXT: clz r2, r2
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: lsls r1, r1, #31
-; CHECK-NEXT: vmov r1, s3
-; CHECK-NEXT: rbit r1, r1
-; CHECK-NEXT: clz r1, r1
-; CHECK-NEXT: add.w r1, r1, #32
+; CHECK-NEXT: adds r2, #32
+; CHECK-NEXT: rbit r0, r0
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
-; CHECK-NEXT: clzne r1, r0
-; CHECK-NEXT: vmov r0, s0
-; CHECK-NEXT: vmov s6, r1
+; CHECK-NEXT: clzne r2, r0
+; CHECK-NEXT: vmov s2, r2
+; CHECK-NEXT: vmov r2, s5
+; CHECK-NEXT: vmov r0, s4
+; CHECK-NEXT: rbit r2, r2
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: rbit r0, r0
+; CHECK-NEXT: clz r2, r2
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: lsls r1, r1, #31
-; CHECK-NEXT: vmov r1, s1
-; CHECK-NEXT: rbit r1, r1
-; CHECK-NEXT: clz r1, r1
-; CHECK-NEXT: add.w r1, r1, #32
+; CHECK-NEXT: adds r2, #32
+; CHECK-NEXT: rbit r0, r0
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
-; CHECK-NEXT: clzne r1, r0
-; CHECK-NEXT: vmov s4, r1
-; CHECK-NEXT: vldr s5, .LCPI4_0
-; CHECK-NEXT: vmov.f32 s7, s5
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: clzne r2, r0
+; CHECK-NEXT: vmov s0, r2
+; CHECK-NEXT: vldr s1, .LCPI4_0
+; CHECK-NEXT: vmov.f32 s3, s1
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
diff --git a/llvm/test/CodeGen/Thumb2/mve-fmas.ll b/llvm/test/CodeGen/Thumb2/mve-fmas.ll
index 241ebc4fe144..a21215848728 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fmas.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fmas.ll
@@ -412,10 +412,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s15, s13
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -423,10 +423,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s12, s0
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
@@ -440,8 +440,8 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s9
; CHECK-MVE-NEXT: vmov.f32 s22, s20
-; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -449,9 +449,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s18, s1
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s18, s5, s9
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
@@ -466,8 +466,8 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s10
; CHECK-MVE-NEXT: vmov.f32 s22, s20
-; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -475,9 +475,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s18, s2
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s18, s6, s10
; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
@@ -493,7 +493,7 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: vmovx.f16 s16, s11
; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: movs r0, #0
@@ -501,10 +501,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.f32 s18, s3
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmla.f16 s18, s7, s11
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -545,10 +545,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s15, s13
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -556,10 +556,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s12, s0
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
@@ -573,8 +573,8 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s9
; CHECK-MVE-NEXT: vmov.f32 s22, s20
-; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -582,9 +582,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s18, s1
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s18, s5, s9
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
@@ -599,8 +599,8 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s10
; CHECK-MVE-NEXT: vmov.f32 s22, s20
-; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -608,9 +608,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s18, s2
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s18, s6, s10
; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
@@ -626,7 +626,7 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: vmovx.f16 s16, s11
; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: movs r0, #0
@@ -634,10 +634,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.f32 s18, s3
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmla.f16 s18, s7, s11
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -678,10 +678,10 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s15, s13
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmls.f16 s15, s14, s12
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -689,10 +689,10 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s12, s0
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmls.f16 s12, s4, s8
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
@@ -706,8 +706,8 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s9
; CHECK-MVE-NEXT: vmov.f32 s22, s20
-; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -715,9 +715,9 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s18, s1
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmls.f16 s18, s5, s9
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
@@ -732,8 +732,8 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s10
; CHECK-MVE-NEXT: vmov.f32 s22, s20
-; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -741,9 +741,9 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s18, s2
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmls.f16 s18, s6, s10
; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
@@ -759,7 +759,7 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: vmovx.f16 s16, s11
; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: movs r0, #0
@@ -767,10 +767,10 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.f32 s18, s3
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmls.f16 s18, s7, s11
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -814,10 +814,10 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s10, s0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s14, s10
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s14, s8, s12
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -825,9 +825,9 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s8, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s8, s4, s12
; CHECK-MVE-NEXT: vseleq.f16 s8, s0, s8
; CHECK-MVE-NEXT: movs r1, #0
@@ -842,7 +842,7 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -853,33 +853,32 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s13, s5, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s9, s1, s13
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmovx.f16 s13, s2
; CHECK-MVE-NEXT: vins.f16 s9, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
-; CHECK-MVE-NEXT: vmovx.f16 s13, s2
+; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vmov.f32 s15, s13
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmov.f32 s13, s2
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.f32 s13, s2
; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s13, s6, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s10, s2, s13
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s10, s14
@@ -893,17 +892,18 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.f32 s13, s3
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmla.f16 s13, s7, s12
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s11, s3, s13
; CHECK-MVE-NEXT: vins.f16 s11, s14
; CHECK-MVE-NEXT: vmov q0, q2
@@ -948,9 +948,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s8, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s8, s14, s10
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s14, s8
@@ -959,9 +959,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s8, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s8, s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s8, s0, s8
; CHECK-MVE-NEXT: movs r1, #0
@@ -976,7 +976,7 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: vmov.f32 s15, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -987,14 +987,14 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s13, s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmov.f32 s15, s12
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s9, s1, s13
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmovx.f16 s13, s2
; CHECK-MVE-NEXT: vins.f16 s9, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
-; CHECK-MVE-NEXT: vmovx.f16 s13, s2
+; CHECK-MVE-NEXT: vmov.f32 s15, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
@@ -1002,41 +1002,41 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmov.f32 s13, s12
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.f32 s13, s12
; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s13, s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmov.f32 s15, s12
; CHECK-MVE-NEXT: vseleq.f16 s10, s2, s13
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s10, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
-; CHECK-MVE-NEXT: vmovx.f16 s13, s3
+; CHECK-MVE-NEXT: vmov.f32 s15, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14
+; CHECK-MVE-NEXT: vmovx.f16 s13, s3
; CHECK-MVE-NEXT: cset r1, ne
+; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmla.f16 s12, s3, s7
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmla.f16 s12, s3, s7
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s11, s3, s12
; CHECK-MVE-NEXT: vins.f16 s11, s14
; CHECK-MVE-NEXT: vmov q0, q2
@@ -1068,50 +1068,50 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v1_pred(<4 x float> %src1, <4 x float
;
; CHECK-MVE-LABEL: vfma32_v1_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s5, #0
+; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vmov.f32 s13, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vmov.f32 s15, s3
+; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s6, #0
+; CHECK-MVE-NEXT: vmov.f32 s15, s2
; CHECK-MVE-NEXT: cset r2, ne
-; CHECK-MVE-NEXT: vmov.f32 s12, s0
+; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: movs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s14, s1
-; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vmov.f32 s13, s2
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vmla.f32 s15, s7, s11
+; CHECK-MVE-NEXT: vmla.f32 s13, s7, s11
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
-; CHECK-MVE-NEXT: lsls r0, r0, #31
-; CHECK-MVE-NEXT: vmla.f32 s14, s5, s9
-; CHECK-MVE-NEXT: vmla.f32 s13, s6, s10
-; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s15
-; CHECK-MVE-NEXT: lsls r0, r3, #31
-; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s13
-; CHECK-MVE-NEXT: lsls r0, r2, #31
-; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s14
-; CHECK-MVE-NEXT: lsls r0, r1, #31
-; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
+; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
+; CHECK-MVE-NEXT: vmla.f32 s15, s6, s10
+; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s13
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s14
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr
entry:
@@ -1138,50 +1138,50 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v2_pred(<4 x float> %src1, <4 x float
;
; CHECK-MVE-LABEL: vfma32_v2_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s5, #0
+; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vmov.f32 s13, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vmov.f32 s15, s3
+; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s6, #0
+; CHECK-MVE-NEXT: vmov.f32 s15, s2
; CHECK-MVE-NEXT: cset r2, ne
-; CHECK-MVE-NEXT: vmov.f32 s12, s0
+; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: movs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s14, s1
-; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vmov.f32 s13, s2
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vmla.f32 s15, s7, s11
+; CHECK-MVE-NEXT: vmla.f32 s13, s7, s11
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
-; CHECK-MVE-NEXT: lsls r0, r0, #31
-; CHECK-MVE-NEXT: vmla.f32 s14, s5, s9
-; CHECK-MVE-NEXT: vmla.f32 s13, s6, s10
-; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s15
-; CHECK-MVE-NEXT: lsls r0, r3, #31
-; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s13
-; CHECK-MVE-NEXT: lsls r0, r2, #31
-; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s14
-; CHECK-MVE-NEXT: lsls r0, r1, #31
-; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
+; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
+; CHECK-MVE-NEXT: vmla.f32 s15, s6, s10
+; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s13
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s14
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr
entry:
@@ -1208,50 +1208,50 @@ define arm_aapcs_vfpcc <4 x float> @vfms32_pred(<4 x float> %src1, <4 x float> %
;
; CHECK-MVE-LABEL: vfms32_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s5, #0
+; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vmov.f32 s13, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vmov.f32 s15, s3
+; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s6, #0
+; CHECK-MVE-NEXT: vmov.f32 s15, s2
; CHECK-MVE-NEXT: cset r2, ne
-; CHECK-MVE-NEXT: vmov.f32 s12, s0
+; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: movs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s14, s1
-; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vmov.f32 s13, s2
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vmls.f32 s15, s7, s11
+; CHECK-MVE-NEXT: vmls.f32 s13, s7, s11
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: vmls.f32 s12, s4, s8
-; CHECK-MVE-NEXT: lsls r0, r0, #31
-; CHECK-MVE-NEXT: vmls.f32 s14, s5, s9
-; CHECK-MVE-NEXT: vmls.f32 s13, s6, s10
-; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s15
-; CHECK-MVE-NEXT: lsls r0, r3, #31
-; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s13
-; CHECK-MVE-NEXT: lsls r0, r2, #31
-; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s14
-; CHECK-MVE-NEXT: lsls r0, r1, #31
-; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vmls.f32 s12, s5, s9
+; CHECK-MVE-NEXT: vmls.f32 s14, s4, s8
+; CHECK-MVE-NEXT: vmls.f32 s15, s6, s10
+; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s13
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s14
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr
entry:
@@ -1281,50 +1281,50 @@ define arm_aapcs_vfpcc <4 x float> @vfmar32_pred(<4 x float> %src1, <4 x float>
;
; CHECK-MVE-LABEL: vfmar32_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s5, #0
+; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vmov.f32 s14, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vmov.f32 s9, s3
+; CHECK-MVE-NEXT: vmov.f32 s10, s1
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s6, #0
+; CHECK-MVE-NEXT: vmov.f32 s9, s2
; CHECK-MVE-NEXT: cset r2, ne
-; CHECK-MVE-NEXT: vmov.f32 s10, s0
+; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: movs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s12, s1
-; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vmov.f32 s14, s2
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vmla.f32 s9, s7, s8
+; CHECK-MVE-NEXT: vmla.f32 s14, s7, s8
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: vmla.f32 s10, s4, s8
-; CHECK-MVE-NEXT: lsls r0, r0, #31
-; CHECK-MVE-NEXT: vmla.f32 s12, s5, s8
-; CHECK-MVE-NEXT: vmla.f32 s14, s6, s8
-; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s9
-; CHECK-MVE-NEXT: lsls r0, r3, #31
-; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s14
-; CHECK-MVE-NEXT: lsls r0, r2, #31
-; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12
-; CHECK-MVE-NEXT: lsls r0, r1, #31
-; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s10
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vmla.f32 s10, s5, s8
+; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
+; CHECK-MVE-NEXT: vmla.f32 s9, s6, s8
+; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s14
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s10
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr
entry:
@@ -1355,30 +1355,30 @@ define arm_aapcs_vfpcc <4 x float> @vfmas32_pred(<4 x float> %src1, <4 x float>
;
; CHECK-MVE-LABEL: vfmas32_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s5, #0
+; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vmov.f32 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s6, #0
+; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vmov.f32 s10, s8
+; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: cset r2, ne
-; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s14, s8
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1386,18 +1386,18 @@ define arm_aapcs_vfpcc <4 x float> @vfmas32_pred(<4 x float> %src1, <4 x float>
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: vmla.f32 s8, s3, s7
-; CHECK-MVE-NEXT: lsls r0, r0, #31
-; CHECK-MVE-NEXT: vmla.f32 s10, s0, s4
-; CHECK-MVE-NEXT: vmla.f32 s12, s1, s5
-; CHECK-MVE-NEXT: vmla.f32 s14, s2, s6
-; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s8
-; CHECK-MVE-NEXT: lsls r0, r3, #31
-; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s14
-; CHECK-MVE-NEXT: lsls r0, r2, #31
-; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12
-; CHECK-MVE-NEXT: lsls r0, r1, #31
-; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s10
+; CHECK-MVE-NEXT: vmla.f32 s14, s3, s7
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vmla.f32 s10, s1, s5
+; CHECK-MVE-NEXT: vmla.f32 s12, s0, s4
+; CHECK-MVE-NEXT: vmla.f32 s8, s2, s6
+; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s14
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s8
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s10
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr
entry:
diff --git a/llvm/test/CodeGen/Thumb2/mve-fmath.ll b/llvm/test/CodeGen/Thumb2/mve-fmath.ll
index 685a966eb3ed..639c1116a9ab 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fmath.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fmath.ll
@@ -1042,62 +1042,62 @@ define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x hal
; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: lsls r0, r0, #31
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #29]
; CHECK-NEXT: vseleq.f16 s8, s4, s6
; CHECK-NEXT: vabs.f16 s4, s0
-; CHECK-NEXT: vabs.f16 s0, s3
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: lsls r0, r0, #31
+; CHECK-NEXT: vabs.f16 s0, s3
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #17]
; CHECK-NEXT: vseleq.f16 s4, s4, s6
+; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vmovx.f16 s8, s1
-; CHECK-NEXT: tst.w r0, #128
-; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: vneg.f16 s10, s8
-; CHECK-NEXT: lsls r0, r0, #31
+; CHECK-NEXT: vabs.f16 s8, s8
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #21]
+; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vabs.f16 s10, s1
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s12, s10
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: lsls r0, r0, #31
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #9]
; CHECK-NEXT: vseleq.f16 s5, s10, s12
+; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vins.f16 s5, s8
; CHECK-NEXT: vmovx.f16 s8, s2
-; CHECK-NEXT: tst.w r0, #128
-; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: vneg.f16 s10, s8
-; CHECK-NEXT: lsls r0, r0, #31
+; CHECK-NEXT: vabs.f16 s8, s8
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #13]
+; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vabs.f16 s10, s2
-; CHECK-NEXT: vneg.f16 s2, s0
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s12, s10
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: lsls r0, r0, #31
+; CHECK-NEXT: vneg.f16 s2, s0
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #1]
; CHECK-NEXT: vseleq.f16 s6, s10, s12
+; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vins.f16 s6, s8
; CHECK-NEXT: vmovx.f16 s8, s3
-; CHECK-NEXT: tst.w r0, #128
-; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: vneg.f16 s10, s8
-; CHECK-NEXT: lsls r0, r0, #31
+; CHECK-NEXT: vabs.f16 s8, s8
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #5]
+; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: lsls r0, r0, #31
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vseleq.f16 s7, s0, s2
; CHECK-NEXT: vins.f16 s7, s8
; CHECK-NEXT: vmov q0, q1
diff --git a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
index f3e45454c692..c14efc566aed 100644
--- a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
@@ -1012,11 +1012,11 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: mul r1, r8, r1
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: cset r4, eq
-; CHECK-NEXT: tst.w r4, #1
+; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csetm r4, ne
; CHECK-NEXT: vmov.32 q4[1], r4
; CHECK-NEXT: vmov q4[2], q4[0], r4, r0
@@ -1026,12 +1026,12 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
; CHECK-NEXT: orr.w r1, r1, r9, asr #31
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: cset r7, eq
; CHECK-NEXT: vmov.32 q0[1], r1
-; CHECK-NEXT: tst.w r7, #1
+; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csetm r7, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r7
; CHECK-NEXT: mla r7, r3, r5, r0
diff --git a/llvm/test/CodeGen/Thumb2/mve-masked-store.ll b/llvm/test/CodeGen/Thumb2/mve-masked-store.ll
index 16e886c887f1..7fe4f9d11991 100644
--- a/llvm/test/CodeGen/Thumb2/mve-masked-store.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-masked-store.ll
@@ -1232,8 +1232,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: cset r1, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-LE-NEXT: and r1, r1, #1
-; CHECK-LE-NEXT: vcmp.f32 s2, #0
; CHECK-LE-NEXT: rsb.w r3, r1, #0
; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
@@ -1242,24 +1240,22 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
; CHECK-LE-NEXT: movgt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: cset r3, ne
+; CHECK-LE-NEXT: vcmp.f32 s2, #0
+; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-LE-NEXT: and r3, r3, #1
-; CHECK-LE-NEXT: vcmp.f32 s3, #0
-; CHECK-LE-NEXT: rsb.w r3, r3, #0
-; CHECK-LE-NEXT: mov.w r2, #0
; CHECK-LE-NEXT: bfi r1, r3, #1, #1
; CHECK-LE-NEXT: mov.w r3, #0
; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: vcmp.f32 s3, #0
; CHECK-LE-NEXT: cset r3, ne
+; CHECK-LE-NEXT: movs r2, #0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r2, #1
; CHECK-LE-NEXT: cmp r2, #0
-; CHECK-LE-NEXT: and r3, r3, #1
; CHECK-LE-NEXT: cset r2, ne
-; CHECK-LE-NEXT: and r2, r2, #1
; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
@@ -1316,8 +1312,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: cset r1, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-BE-NEXT: and r1, r1, #1
-; CHECK-BE-NEXT: vcmp.f32 s5, #0
; CHECK-BE-NEXT: rsb.w r3, r1, #0
; CHECK-BE-NEXT: mov.w r1, #0
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
@@ -1326,25 +1320,23 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: cset r3, ne
+; CHECK-BE-NEXT: vcmp.f32 s5, #0
+; CHECK-BE-NEXT: rsbs r3, r3, #0
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-BE-NEXT: and r3, r3, #1
-; CHECK-BE-NEXT: vcmp.f32 s4, #0
-; CHECK-BE-NEXT: rsb.w r3, r3, #0
-; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: cset r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r2, #1
; CHECK-BE-NEXT: cmp r2, #0
-; CHECK-BE-NEXT: and r3, r3, #1
+; CHECK-BE-NEXT: rsb.w r3, r3, #0
; CHECK-BE-NEXT: cset r2, ne
-; CHECK-BE-NEXT: and r2, r2, #1
-; CHECK-BE-NEXT: rsbs r3, r3, #0
+; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
; CHECK-BE-NEXT: rsbs r2, r2, #0
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
@@ -1404,8 +1396,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: cset r1, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-LE-NEXT: and r1, r1, #1
-; CHECK-LE-NEXT: vcmp.f32 s2, #0
; CHECK-LE-NEXT: rsb.w r3, r1, #0
; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
@@ -1414,24 +1404,22 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
; CHECK-LE-NEXT: movgt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: cset r3, ne
+; CHECK-LE-NEXT: vcmp.f32 s2, #0
+; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-LE-NEXT: and r3, r3, #1
-; CHECK-LE-NEXT: vcmp.f32 s3, #0
-; CHECK-LE-NEXT: rsb.w r3, r3, #0
-; CHECK-LE-NEXT: mov.w r2, #0
; CHECK-LE-NEXT: bfi r1, r3, #1, #1
; CHECK-LE-NEXT: mov.w r3, #0
; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: vcmp.f32 s3, #0
; CHECK-LE-NEXT: cset r3, ne
+; CHECK-LE-NEXT: movs r2, #0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r2, #1
; CHECK-LE-NEXT: cmp r2, #0
-; CHECK-LE-NEXT: and r3, r3, #1
; CHECK-LE-NEXT: cset r2, ne
-; CHECK-LE-NEXT: and r2, r2, #1
; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
@@ -1488,8 +1476,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: cset r1, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-BE-NEXT: and r1, r1, #1
-; CHECK-BE-NEXT: vcmp.f32 s5, #0
; CHECK-BE-NEXT: rsb.w r3, r1, #0
; CHECK-BE-NEXT: mov.w r1, #0
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
@@ -1498,25 +1484,23 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: cset r3, ne
+; CHECK-BE-NEXT: vcmp.f32 s5, #0
+; CHECK-BE-NEXT: rsbs r3, r3, #0
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-BE-NEXT: and r3, r3, #1
-; CHECK-BE-NEXT: vcmp.f32 s4, #0
-; CHECK-BE-NEXT: rsb.w r3, r3, #0
-; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: cset r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r2, #1
; CHECK-BE-NEXT: cmp r2, #0
-; CHECK-BE-NEXT: and r3, r3, #1
+; CHECK-BE-NEXT: rsb.w r3, r3, #0
; CHECK-BE-NEXT: cset r2, ne
-; CHECK-BE-NEXT: and r2, r2, #1
-; CHECK-BE-NEXT: rsbs r3, r3, #0
+; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
; CHECK-BE-NEXT: rsbs r2, r2, #0
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
@@ -1576,8 +1560,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: cset r1, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-LE-NEXT: and r1, r1, #1
-; CHECK-LE-NEXT: vcmp.f32 s2, #0
; CHECK-LE-NEXT: rsb.w r3, r1, #0
; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
@@ -1586,24 +1568,22 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
; CHECK-LE-NEXT: movgt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: cset r3, ne
+; CHECK-LE-NEXT: vcmp.f32 s2, #0
+; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-LE-NEXT: and r3, r3, #1
-; CHECK-LE-NEXT: vcmp.f32 s3, #0
-; CHECK-LE-NEXT: rsb.w r3, r3, #0
-; CHECK-LE-NEXT: mov.w r2, #0
; CHECK-LE-NEXT: bfi r1, r3, #1, #1
; CHECK-LE-NEXT: mov.w r3, #0
; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: vcmp.f32 s3, #0
; CHECK-LE-NEXT: cset r3, ne
+; CHECK-LE-NEXT: movs r2, #0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r2, #1
; CHECK-LE-NEXT: cmp r2, #0
-; CHECK-LE-NEXT: and r3, r3, #1
; CHECK-LE-NEXT: cset r2, ne
-; CHECK-LE-NEXT: and r2, r2, #1
; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
@@ -1668,8 +1648,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: cset r1, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-BE-NEXT: and r1, r1, #1
-; CHECK-BE-NEXT: vcmp.f32 s5, #0
; CHECK-BE-NEXT: rsb.w r3, r1, #0
; CHECK-BE-NEXT: mov.w r1, #0
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
@@ -1678,25 +1656,23 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: cset r3, ne
+; CHECK-BE-NEXT: vcmp.f32 s5, #0
+; CHECK-BE-NEXT: rsbs r3, r3, #0
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-BE-NEXT: and r3, r3, #1
-; CHECK-BE-NEXT: vcmp.f32 s4, #0
-; CHECK-BE-NEXT: rsb.w r3, r3, #0
-; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: cset r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r2, #1
; CHECK-BE-NEXT: cmp r2, #0
-; CHECK-BE-NEXT: and r3, r3, #1
+; CHECK-BE-NEXT: rsb.w r3, r3, #0
; CHECK-BE-NEXT: cset r2, ne
-; CHECK-BE-NEXT: and r2, r2, #1
-; CHECK-BE-NEXT: rsbs r3, r3, #0
+; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
; CHECK-BE-NEXT: rsbs r2, r2, #0
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
diff --git a/llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll b/llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll
index cddbfc4e95f3..71bdd6b0d86b 100644
--- a/llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll
@@ -20,11 +20,9 @@ define void @tailpred(half* nocapture readonly %pSrcA, half* nocapture readonly
; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: cmp r5, r2
; CHECK-NEXT: cset r5, hi
-; CHECK-NEXT: ands r4, r5
-; CHECK-NEXT: lsls r4, r4, #31
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: andeq.w r5, lr, r12
-; CHECK-NEXT: lslseq.w r5, r5, #31
+; CHECK-NEXT: tst r5, r4
+; CHECK-NEXT: it eq
+; CHECK-NEXT: andseq.w r5, lr, r12
; CHECK-NEXT: beq .LBB0_4
; CHECK-NEXT: @ %bb.2: @ %while.body.preheader
; CHECK-NEXT: dls lr, r3
@@ -130,11 +128,9 @@ define void @notailpred(half* nocapture readonly %pSrcA, half* nocapture readonl
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: cmp r4, r2
; CHECK-NEXT: cset r4, hi
-; CHECK-NEXT: ands r5, r4
-; CHECK-NEXT: lsls r5, r5, #31
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: andeq r7, r6
-; CHECK-NEXT: lslseq.w r7, r7, #31
+; CHECK-NEXT: tst r4, r5
+; CHECK-NEXT: it eq
+; CHECK-NEXT: andseq.w r7, r7, r6
; CHECK-NEXT: beq .LBB1_7
; CHECK-NEXT: .LBB1_3:
; CHECK-NEXT: mov r5, r3
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-and.ll b/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
index 17d83c8e0988..1a3993097fa8 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
@@ -581,11 +581,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
@@ -615,7 +615,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s8
@@ -623,7 +623,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
@@ -632,11 +632,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
@@ -663,7 +663,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: vmov r3, s5
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: vmov r3, s4
@@ -671,7 +671,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q2[2], q2[0], r0, r2
; CHECK-NEXT: vmov q2[3], q2[1], r0, r2
@@ -680,11 +680,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll b/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
index 5f7f14fbd23e..53f2ea04674f 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
@@ -397,7 +397,7 @@ define arm_aapcs_vfpcc i2 @bitcast_from_v2i1(<2 x i64> %a) {
; CHECK-LE-NEXT: cset r0, eq
; CHECK-LE-NEXT: orrs r1, r2
; CHECK-LE-NEXT: cset r1, eq
-; CHECK-LE-NEXT: ands r1, r1, #1
+; CHECK-LE-NEXT: cmp r1, #0
; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r1, #1
; CHECK-LE-NEXT: bfi r1, r0, #0, #1
@@ -418,7 +418,7 @@ define arm_aapcs_vfpcc i2 @bitcast_from_v2i1(<2 x i64> %a) {
; CHECK-BE-NEXT: cset r0, eq
; CHECK-BE-NEXT: orrs r1, r2
; CHECK-BE-NEXT: cset r1, eq
-; CHECK-BE-NEXT: ands r1, r1, #1
+; CHECK-BE-NEXT: cmp r1, #0
; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r1, #1
; CHECK-BE-NEXT: bfi r1, r0, #0, #1
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll b/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
index 4d0568a675be..dc9852060b1a 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
@@ -8,7 +8,6 @@ define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a,
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #4
; CHECK-NEXT: vmsr p0, r1
@@ -27,7 +26,6 @@ define arm_aapcs_vfpcc <4 x i32> @build_var3_v4i1(i32 %s, i32 %t, <4 x i32> %a,
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #12, #4
; CHECK-NEXT: vmsr p0, r1
@@ -45,7 +43,6 @@ define arm_aapcs_vfpcc <4 x i32> @build_varN_v4i1(i32 %s, i32 %t, <4 x i32> %a,
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q0, q1
@@ -65,7 +62,6 @@ define arm_aapcs_vfpcc <8 x i16> @build_var0_v8i1(i32 %s, i32 %t, <8 x i16> %a,
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #2
; CHECK-NEXT: vmsr p0, r1
@@ -84,7 +80,6 @@ define arm_aapcs_vfpcc <8 x i16> @build_var3_v8i1(i32 %s, i32 %t, <8 x i16> %a,
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #6, #2
; CHECK-NEXT: vmsr p0, r1
@@ -102,7 +97,6 @@ define arm_aapcs_vfpcc <8 x i16> @build_varN_v8i1(i32 %s, i32 %t, <8 x i16> %a,
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q0, q1
@@ -122,7 +116,6 @@ define arm_aapcs_vfpcc <16 x i8> @build_var0_v16i1(i32 %s, i32 %t, <16 x i8> %a,
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #1
; CHECK-NEXT: vmsr p0, r1
@@ -141,7 +134,6 @@ define arm_aapcs_vfpcc <16 x i8> @build_var3_v16i1(i32 %s, i32 %t, <16 x i8> %a,
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #3, #1
; CHECK-NEXT: vmsr p0, r1
@@ -159,7 +151,6 @@ define arm_aapcs_vfpcc <16 x i8> @build_varN_v16i1(i32 %s, i32 %t, <16 x i8> %a,
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q0, q1
@@ -178,7 +169,6 @@ define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a,
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov s8, r0
; CHECK-NEXT: vldr s10, .LCPI9_0
@@ -204,7 +194,6 @@ define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a,
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov s10, r0
; CHECK-NEXT: vldr s8, .LCPI10_0
@@ -230,7 +219,6 @@ define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a,
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: cset r0, lo
-; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vdup.32 q2, r0
; CHECK-NEXT: vbic q1, q1, q2
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll b/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
index cfecd4c5f14e..d859e20ffd61 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
@@ -326,7 +326,7 @@ define arm_aapcs_vfpcc void @store_v2i1(<2 x i1> *%dst, <2 x i64> %a) {
; CHECK-LE-NEXT: cset r1, eq
; CHECK-LE-NEXT: orrs r2, r3
; CHECK-LE-NEXT: cset r2, eq
-; CHECK-LE-NEXT: ands r2, r2, #1
+; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r2, #1
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
@@ -345,7 +345,7 @@ define arm_aapcs_vfpcc void @store_v2i1(<2 x i1> *%dst, <2 x i64> %a) {
; CHECK-BE-NEXT: cset r1, eq
; CHECK-BE-NEXT: orrs r2, r3
; CHECK-BE-NEXT: cset r2, eq
-; CHECK-BE-NEXT: ands r2, r2, #1
+; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r2, #1
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-not.ll b/llvm/test/CodeGen/Thumb2/mve-pred-not.ll
index 9ed3add2fd16..4ddc86632a99 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-not.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-not.ll
@@ -329,11 +329,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
@@ -357,11 +357,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-or.ll b/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
index d498d7cb6f53..37fe00057b06 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
@@ -383,12 +383,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
@@ -397,11 +397,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
@@ -432,7 +432,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s8
@@ -440,7 +440,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
@@ -449,11 +449,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll b/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
index 2223afa94395..9fba17f42115 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
@@ -78,12 +78,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
@@ -92,12 +92,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
@@ -107,11 +107,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
@@ -208,12 +208,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpnez_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
@@ -222,12 +222,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpnez_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
@@ -237,11 +237,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpnez_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
@@ -446,24 +446,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1_i1(<2 x i64> %a, <2 x i64> %b, i64
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: csetm r12, ne
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: csetm r4, ne
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: csetm lr, ne
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: beq .LBB15_2
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll b/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
index 6c13200a2d55..6f336eb33658 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
@@ -463,12 +463,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
@@ -477,11 +477,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
@@ -512,7 +512,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s8
@@ -520,7 +520,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
@@ -529,11 +529,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
diff --git a/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll b/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
index 172213cab0c5..105330c0e54c 100644
--- a/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
@@ -49,9 +49,9 @@ define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2)
; CHECK-NEXT: eors r1, r0
; CHECK-NEXT: bic.w r1, r1, r12
; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: cset r1, mi
-; CHECK-NEXT: ands r12, r1, #1
; CHECK-NEXT: vmov r1, s1
+; CHECK-NEXT: cset r12, mi
+; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: asrne r2, r0, #31
; CHECK-NEXT: adds r4, r4, r5
@@ -62,19 +62,19 @@ define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2)
; CHECK-NEXT: bic.w r1, r1, lr
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, mi
-; CHECK-NEXT: ands r1, r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: asrne r4, r3, #31
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov q0[2], q0[0], r4, r2
; CHECK-NEXT: cset r2, mi
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cinv r2, r5, eq
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r2, r0, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r2, mi
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cinv r2, r5, eq
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csel r1, r2, r3, ne
@@ -201,9 +201,9 @@ define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2)
; CHECK-NEXT: sbc.w r0, r1, r0
; CHECK-NEXT: eors r1, r0
; CHECK-NEXT: ands.w r1, r1, r12
-; CHECK-NEXT: cset r1, mi
-; CHECK-NEXT: ands r12, r1, #1
; CHECK-NEXT: vmov r1, s1
+; CHECK-NEXT: cset r12, mi
+; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: asrne r2, r0, #31
; CHECK-NEXT: subs r4, r5, r4
@@ -213,19 +213,19 @@ define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2)
; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: ands.w r1, r1, lr
; CHECK-NEXT: cset r1, mi
-; CHECK-NEXT: ands r1, r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: asrne r4, r3, #31
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov q0[2], q0[0], r4, r2
; CHECK-NEXT: cset r2, mi
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cinv r2, r5, eq
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r2, r0, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r2, mi
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cinv r2, r5, eq
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csel r1, r2, r3, ne
diff --git a/llvm/test/CodeGen/Thumb2/mve-selectcc.ll b/llvm/test/CodeGen/Thumb2/mve-selectcc.ll
index b4f5d8d8fa3f..0df34c7ec173 100644
--- a/llvm/test/CodeGen/Thumb2/mve-selectcc.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-selectcc.ll
@@ -218,7 +218,7 @@ define i32 @e() {
; CHECK-NEXT: vadd.i32 q2, q2, q1
; CHECK-NEXT: cmp r0, #8
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs.w r2, r0, #8
; CHECK-NEXT: vdup.32 q3, r1
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmp.ll b/llvm/test/CodeGen/Thumb2/mve-vcmp.ll
index aeffc39b26f8..03bd26af05f4 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmp.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmp.ll
@@ -378,14 +378,14 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, <2 x i64> %srcb,
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: eors r2, r3
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
@@ -413,14 +413,14 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, <2 x i64> %srcb,
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: eors r2, r3
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
@@ -448,12 +448,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
@@ -479,12 +479,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov q3[3], q3[1], r1, lr
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
@@ -492,11 +492,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
index fb81aca1f7fa..a94079d65921 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
@@ -5,24 +5,24 @@
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -33,13 +33,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -57,23 +57,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
@@ -86,7 +86,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
@@ -95,13 +95,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -120,24 +120,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -148,13 +148,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -172,24 +172,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -200,13 +200,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -224,24 +224,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -252,13 +252,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -276,24 +276,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -304,13 +304,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -328,23 +328,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
@@ -357,7 +357,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
@@ -366,13 +366,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -391,24 +391,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -419,13 +419,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -443,24 +443,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -471,13 +471,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -495,24 +495,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -523,13 +523,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -547,24 +547,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -575,13 +575,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -599,24 +599,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -627,13 +627,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -651,24 +651,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -679,13 +679,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -704,24 +704,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -732,13 +732,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -772,7 +772,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -783,9 +783,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -797,18 +797,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -820,18 +820,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -843,14 +843,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -885,7 +885,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0
@@ -899,9 +899,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -914,7 +914,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
@@ -926,9 +926,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -941,7 +941,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
@@ -953,9 +953,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -968,7 +968,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -978,7 +978,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1013,7 +1013,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1024,9 +1024,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1038,18 +1038,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1061,18 +1061,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1084,14 +1084,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1125,7 +1125,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1136,9 +1136,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1150,18 +1150,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1173,18 +1173,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1196,14 +1196,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1237,7 +1237,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1248,9 +1248,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1262,18 +1262,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1285,18 +1285,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1308,14 +1308,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1349,7 +1349,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1360,9 +1360,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1374,18 +1374,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1397,18 +1397,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1420,14 +1420,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1462,7 +1462,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0
@@ -1476,9 +1476,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1491,7 +1491,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
@@ -1503,9 +1503,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1518,7 +1518,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
@@ -1530,9 +1530,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1545,7 +1545,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1555,7 +1555,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1590,7 +1590,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1601,9 +1601,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1615,18 +1615,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1638,18 +1638,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1661,14 +1661,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1702,7 +1702,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1713,9 +1713,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1727,18 +1727,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1750,18 +1750,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1773,14 +1773,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1814,7 +1814,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1825,9 +1825,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1839,18 +1839,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1862,18 +1862,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1885,14 +1885,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1926,7 +1926,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1937,9 +1937,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1951,18 +1951,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1974,18 +1974,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -1997,14 +1997,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -2038,7 +2038,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -2049,9 +2049,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -2063,18 +2063,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -2086,18 +2086,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -2109,14 +2109,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -2150,7 +2150,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -2161,9 +2161,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -2175,18 +2175,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -2198,18 +2198,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -2221,14 +2221,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
@@ -2263,7 +2263,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -2274,9 +2274,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -2288,18 +2288,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -2311,18 +2311,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s22, s3
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
@@ -2334,14 +2334,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov q0, q4
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
index 5b4d3c5220d4..e47207594a7a 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
@@ -5,24 +5,24 @@
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -33,13 +33,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -60,23 +60,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
@@ -89,7 +89,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
@@ -98,13 +98,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -126,24 +126,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -154,13 +154,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -181,24 +181,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -209,13 +209,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -236,24 +236,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -264,13 +264,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -291,24 +291,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -319,13 +319,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -346,23 +346,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
@@ -375,7 +375,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
@@ -384,13 +384,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -412,24 +412,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -440,13 +440,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -467,24 +467,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -495,13 +495,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -522,24 +522,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -550,13 +550,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -577,24 +577,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -605,13 +605,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -632,24 +632,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -660,13 +660,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -687,24 +687,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -715,13 +715,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -743,24 +743,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -771,13 +771,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, float %src2
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -814,19 +814,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -837,18 +837,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -859,18 +859,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -881,14 +881,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -926,7 +926,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
@@ -938,10 +938,10 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -954,20 +954,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -980,20 +980,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1006,7 +1006,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
@@ -1015,7 +1015,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1053,19 +1053,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1076,18 +1076,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1098,18 +1098,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1120,14 +1120,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1164,19 +1164,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1187,18 +1187,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1209,18 +1209,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1231,14 +1231,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1275,19 +1275,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1298,18 +1298,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1320,18 +1320,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1342,14 +1342,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1386,19 +1386,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1409,18 +1409,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1431,18 +1431,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1453,14 +1453,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1498,7 +1498,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
@@ -1510,10 +1510,10 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1526,20 +1526,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1552,20 +1552,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1578,7 +1578,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
@@ -1587,7 +1587,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1625,19 +1625,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1648,18 +1648,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1670,18 +1670,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1692,14 +1692,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1736,19 +1736,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1759,18 +1759,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1781,18 +1781,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1803,14 +1803,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1847,19 +1847,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1870,18 +1870,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1892,18 +1892,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1914,14 +1914,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -1958,19 +1958,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1981,18 +1981,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -2003,18 +2003,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -2025,14 +2025,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -2069,19 +2069,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -2092,18 +2092,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -2114,18 +2114,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -2136,14 +2136,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -2180,19 +2180,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -2203,18 +2203,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -2225,18 +2225,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -2247,14 +2247,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -2292,19 +2292,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -2315,18 +2315,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -2337,18 +2337,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -2359,14 +2359,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -2394,24 +2394,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2422,13 +2422,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -2449,23 +2449,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
@@ -2478,7 +2478,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
@@ -2487,13 +2487,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -2515,24 +2515,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2543,13 +2543,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -2570,24 +2570,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2598,13 +2598,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -2625,24 +2625,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2653,13 +2653,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -2680,24 +2680,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2708,13 +2708,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -2735,23 +2735,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
@@ -2764,7 +2764,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
@@ -2773,13 +2773,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -2801,24 +2801,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2829,13 +2829,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -2856,24 +2856,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2884,13 +2884,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -2911,24 +2911,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2939,13 +2939,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -2966,24 +2966,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2994,13 +2994,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -3021,24 +3021,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -3049,13 +3049,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -3076,24 +3076,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -3104,13 +3104,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -3132,24 +3132,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -3160,13 +3160,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, float %sr
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -3203,19 +3203,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3226,18 +3226,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3248,18 +3248,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3270,14 +3270,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -3315,7 +3315,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
@@ -3327,10 +3327,10 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3343,20 +3343,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3369,20 +3369,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3395,7 +3395,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
@@ -3404,7 +3404,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -3442,19 +3442,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3465,18 +3465,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3487,18 +3487,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3509,14 +3509,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -3553,19 +3553,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3576,18 +3576,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3598,18 +3598,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3620,14 +3620,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -3664,19 +3664,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3687,18 +3687,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3709,18 +3709,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3731,14 +3731,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -3775,19 +3775,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3798,18 +3798,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3820,18 +3820,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3842,14 +3842,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -3887,7 +3887,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
@@ -3899,10 +3899,10 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3915,20 +3915,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3941,20 +3941,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -3967,7 +3967,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
@@ -3976,7 +3976,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -4014,19 +4014,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4037,18 +4037,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4059,18 +4059,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4081,14 +4081,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -4125,19 +4125,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4148,18 +4148,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4170,18 +4170,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4192,14 +4192,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -4236,19 +4236,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4259,18 +4259,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4281,18 +4281,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4303,14 +4303,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -4347,19 +4347,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4370,18 +4370,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4392,18 +4392,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4414,14 +4414,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -4458,19 +4458,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4481,18 +4481,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4503,18 +4503,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4525,14 +4525,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -4569,19 +4569,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4592,18 +4592,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4614,18 +4614,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4636,14 +4636,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -4681,19 +4681,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4704,18 +4704,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4726,18 +4726,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
@@ -4748,14 +4748,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
@@ -4795,19 +4795,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16_bc(<8 x half> %src, half %src2
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s13
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -4818,18 +4818,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16_bc(<8 x half> %src, half %src2
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s14
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -4840,18 +4840,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16_bc(<8 x half> %src, half %src2
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s5, s15
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -4862,14 +4862,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16_bc(<8 x half> %src, half %src2
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov q0, q4
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
index 5021aa2f5fc9..eee5c5b249e1 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
@@ -5,24 +5,24 @@
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -33,13 +33,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -57,23 +57,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
@@ -86,7 +86,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
@@ -95,13 +95,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -120,24 +120,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -148,13 +148,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -172,24 +172,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -200,13 +200,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -224,24 +224,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -252,13 +252,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -276,24 +276,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -304,13 +304,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -328,23 +328,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
@@ -357,7 +357,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
@@ -366,13 +366,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -391,24 +391,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -419,13 +419,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -443,24 +443,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -471,13 +471,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -495,24 +495,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -523,13 +523,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -547,24 +547,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -575,13 +575,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -599,24 +599,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -627,13 +627,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -651,24 +651,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s1
+; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s2
+; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s3
+; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -679,13 +679,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -704,24 +704,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s1
+; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s2
+; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s3
+; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -732,13 +732,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -772,19 +772,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -795,18 +795,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -817,18 +817,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -839,14 +839,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -881,7 +881,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
@@ -893,10 +893,10 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -909,20 +909,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -935,20 +935,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -961,7 +961,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
@@ -970,7 +970,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -1005,19 +1005,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1028,18 +1028,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1050,18 +1050,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1072,14 +1072,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -1113,19 +1113,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1136,18 +1136,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1158,18 +1158,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1180,14 +1180,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -1221,19 +1221,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1244,18 +1244,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1266,18 +1266,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1288,14 +1288,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -1329,19 +1329,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1352,18 +1352,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1374,18 +1374,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1396,14 +1396,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -1438,7 +1438,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
@@ -1450,10 +1450,10 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1466,20 +1466,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1492,20 +1492,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1518,7 +1518,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
@@ -1527,7 +1527,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -1562,19 +1562,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1585,18 +1585,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1607,18 +1607,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1629,14 +1629,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -1670,19 +1670,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1693,18 +1693,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1715,18 +1715,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1737,14 +1737,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -1778,19 +1778,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1801,18 +1801,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1823,18 +1823,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1845,14 +1845,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -1886,19 +1886,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1909,18 +1909,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1931,18 +1931,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -1953,14 +1953,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -1994,19 +1994,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -2017,18 +2017,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -2039,18 +2039,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -2061,14 +2061,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -2102,19 +2102,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -2125,18 +2125,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -2147,18 +2147,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -2169,14 +2169,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -2211,19 +2211,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -2234,18 +2234,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -2256,18 +2256,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -2278,14 +2278,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -2310,24 +2310,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2338,13 +2338,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2362,23 +2362,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
@@ -2391,7 +2391,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
@@ -2400,13 +2400,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2425,24 +2425,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2453,13 +2453,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2477,24 +2477,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2505,13 +2505,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2529,24 +2529,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2557,13 +2557,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2581,24 +2581,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2609,13 +2609,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2633,23 +2633,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
@@ -2662,7 +2662,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
@@ -2671,13 +2671,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2696,24 +2696,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2724,13 +2724,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2748,24 +2748,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2776,13 +2776,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2800,24 +2800,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2828,13 +2828,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2852,24 +2852,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2880,13 +2880,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2904,24 +2904,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2932,13 +2932,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2956,24 +2956,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s1
+; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s2
+; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s3
+; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -2984,13 +2984,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -3009,24 +3009,24 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s1, s1
+; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: vcmp.f32 s2, s2
+; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: vcmp.f32 s3, s3
+; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
@@ -3037,13 +3037,13 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: lsls r0, r3, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: lsls r0, r2, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: lsls r0, r1, #31
+; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -3077,19 +3077,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3100,18 +3100,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3122,18 +3122,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3144,14 +3144,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -3186,7 +3186,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
@@ -3198,10 +3198,10 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3214,20 +3214,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3240,20 +3240,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3266,7 +3266,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
@@ -3275,7 +3275,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -3310,19 +3310,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3333,18 +3333,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3355,18 +3355,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3377,14 +3377,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -3418,19 +3418,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3441,18 +3441,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3463,18 +3463,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3485,14 +3485,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -3526,19 +3526,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3549,18 +3549,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3571,18 +3571,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3593,14 +3593,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -3634,19 +3634,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3657,18 +3657,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3679,18 +3679,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3701,14 +3701,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -3743,7 +3743,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
@@ -3755,10 +3755,10 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3771,20 +3771,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3797,20 +3797,20 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3823,7 +3823,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
@@ -3832,7 +3832,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -3867,19 +3867,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3890,18 +3890,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3912,18 +3912,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3934,14 +3934,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -3975,19 +3975,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -3998,18 +3998,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -4020,18 +4020,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -4042,14 +4042,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -4083,19 +4083,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -4106,18 +4106,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -4128,18 +4128,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -4150,14 +4150,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -4191,19 +4191,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -4214,18 +4214,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -4236,18 +4236,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -4258,14 +4258,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -4299,19 +4299,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -4322,18 +4322,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -4344,18 +4344,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
@@ -4366,14 +4366,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -4407,19 +4407,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -4430,18 +4430,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -4452,18 +4452,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -4474,14 +4474,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
@@ -4516,19 +4516,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
-; CHECK-MVE-NEXT: lsls r1, r1, #31
-; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s9
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
-; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -4539,18 +4539,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -4561,18 +4561,18 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: mov.w r1, #0
-; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: vmovx.f16 s18, s11
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
-; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
@@ -4583,14 +4583,14 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne
-; CHECK-MVE-NEXT: lsls r1, r1, #31
+; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne
-; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov q0, q3
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
index a8f04d389e02..aaf97a6503a2 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
@@ -440,14 +440,14 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: eors r0, r3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2
@@ -473,14 +473,14 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: eors r0, r3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2
@@ -510,12 +510,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
@@ -541,12 +541,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov q3[3], q3[1], r1, lr
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
@@ -554,11 +554,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
@@ -1021,14 +1021,14 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eq_v2i64(<2 x i64> %src, i64 %src2, <2
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: eors r0, r3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2
@@ -1054,14 +1054,14 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eq_v2i32(<2 x i64> %src, i64 %src2, <2
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: eors r0, r3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2
@@ -1091,12 +1091,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b,
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
@@ -1122,12 +1122,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b,
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov q3[3], q3[1], r1, lr
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
@@ -1135,11 +1135,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b,
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, ne
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
index 78df48775ebe..1e8fbb3700b5 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
@@ -367,11 +367,11 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eqz_v2i64(<2 x i64> %src, <2 x i64> %a, <
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
@@ -394,11 +394,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eqz_v2i32(<2 x i64> %src, <2 x i32> %a, <
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
@@ -781,11 +781,11 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eqz_v2i64(<2 x i64> %src, <2 x i64> %a,
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
@@ -808,11 +808,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eqz_v2i32(<2 x i64> %src, <2 x i32> %a,
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
index 0d6d88c13ab7..5d6a8a9ba7b6 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
@@ -51,11 +51,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_zext(<2 x i32> %x, <2 x i32> %b) {
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
@@ -88,11 +88,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_sext(<2 x i32> %x, <2 x i32> %b) {
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
@@ -452,11 +452,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_zext(<2 x i16> %x, <2 x i16> %b) {
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
@@ -485,11 +485,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_sext(<2 x i16> %x, <2 x i16> %b) {
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
@@ -1534,11 +1534,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_zext(<2 x i8> %x, <2 x i8> %b) {
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
@@ -1567,11 +1567,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_sext(<2 x i8> %x, <2 x i8> %b) {
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
@@ -1608,11 +1608,11 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64(<2 x i64> %x, <2 x i64> %b) {
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
@@ -1686,11 +1686,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_zext(<2 x i32> %x, <2 x i32> %b,
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
@@ -1728,11 +1728,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_sext(<2 x i32> %x, <2 x i32> %b,
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
@@ -2078,11 +2078,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_zext(<2 x i16> %x, <2 x i16> %b,
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
@@ -2116,11 +2116,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_sext(<2 x i16> %x, <2 x i16> %b,
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
@@ -2812,11 +2812,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_zext(<2 x i8> %x, <2 x i8> %b, i6
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
@@ -2850,11 +2850,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_sext(<2 x i8> %x, <2 x i8> %b, i6
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
@@ -2896,11 +2896,11 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64_acc(<2 x i64> %x, <2 x i64> %b, i64
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: orrs.w r3, r3, r12
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
index 69aa577149ca..1222a2d3cb85 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
@@ -55,11 +55,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_zext(<2 x i32> %x, <2 x i32> %y, <2
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
@@ -89,11 +89,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_sext(<2 x i32> %x, <2 x i32> %y, <2
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
@@ -339,11 +339,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_zext(<2 x i16> %x, <2 x i16> %y, <2
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
@@ -379,11 +379,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_sext(<2 x i16> %x, <2 x i16> %y, <2
; CHECK-NEXT: sxth r3, r3
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: smull r2, r3, r3, r2
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
@@ -1489,11 +1489,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_zext(<2 x i8> %x, <2 x i8> %y, <2 x i
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
@@ -1529,11 +1529,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_sext(<2 x i8> %x, <2 x i8> %y, <2 x i
; CHECK-NEXT: sxtb r3, r3
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: smull r2, r3, r3, r2
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
@@ -1589,11 +1589,11 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: tst.w r0, #1
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: tst.w r1, #1
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
@@ -1672,11 +1672,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_zext(<2 x i32> %x, <2 x i32> %y,
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q0[2], q0[0], r3, r2
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2
@@ -1711,11 +1711,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_sext(<2 x i32> %x, <2 x i32> %y,
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q0[2], q0[0], r3, r2
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2
@@ -1938,11 +1938,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_zext(<2 x i16> %x, <2 x i16> %y,
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
@@ -1978,11 +1978,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_sext(<2 x i16> %x, <2 x i16> %y,
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q2[2], q2[0], r3, r2
; CHECK-NEXT: vmov q2[3], q2[1], r3, r2
@@ -2892,11 +2892,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_zext(<2 x i8> %x, <2 x i8> %y, <2
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
@@ -2932,11 +2932,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_sext(<2 x i8> %x, <2 x i8> %y, <2
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q2[2], q2[0], r3, r2
; CHECK-NEXT: vmov q2[3], q2[1], r3, r2
@@ -3000,11 +3000,11 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64_acc(<2 x i64> %x, <2 x i64> %y, <2 x
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: tst.w r2, #1
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: orrs r3, r7
; CHECK-NEXT: cset r3, eq
-; CHECK-NEXT: tst.w r3, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q0[2], q0[0], r3, r2
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
index 2ca8f93f5385..46b950e7e59a 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
@@ -521,7 +521,6 @@ define arm_aapcs_vfpcc <4 x i32> @i1and_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c)
; CHECKLE-NEXT: cmp r0, #0
; CHECKLE-NEXT: mov.w r1, #15
; CHECKLE-NEXT: cset r0, eq
-; CHECKLE-NEXT: and r0, r0, #1
; CHECKLE-NEXT: rsbs r0, r0, #0
; CHECKLE-NEXT: ands r0, r1
; CHECKLE-NEXT: vmsr p0, r0
@@ -534,9 +533,8 @@ define arm_aapcs_vfpcc <4 x i32> @i1and_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c)
; CHECKBE-NEXT: mov.w r1, #15
; CHECKBE-NEXT: cset r0, eq
; CHECKBE-NEXT: vrev64.32 q2, q1
-; CHECKBE-NEXT: and r0, r0, #1
-; CHECKBE-NEXT: vrev64.32 q1, q0
; CHECKBE-NEXT: rsbs r0, r0, #0
+; CHECKBE-NEXT: vrev64.32 q1, q0
; CHECKBE-NEXT: ands r0, r1
; CHECKBE-NEXT: vmsr p0, r0
; CHECKBE-NEXT: vpsel q1, q1, q2
@@ -557,7 +555,6 @@ define arm_aapcs_vfpcc <4 x i32> @i1or_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c)
; CHECKLE-NEXT: cmp r0, #0
; CHECKLE-NEXT: mov.w r1, #15
; CHECKLE-NEXT: cset r0, eq
-; CHECKLE-NEXT: and r0, r0, #1
; CHECKLE-NEXT: rsbs r0, r0, #0
; CHECKLE-NEXT: orrs r0, r1
; CHECKLE-NEXT: vmsr p0, r0
@@ -570,9 +567,8 @@ define arm_aapcs_vfpcc <4 x i32> @i1or_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c)
; CHECKBE-NEXT: mov.w r1, #15
; CHECKBE-NEXT: cset r0, eq
; CHECKBE-NEXT: vrev64.32 q2, q1
-; CHECKBE-NEXT: and r0, r0, #1
-; CHECKBE-NEXT: vrev64.32 q1, q0
; CHECKBE-NEXT: rsbs r0, r0, #0
+; CHECKBE-NEXT: vrev64.32 q1, q0
; CHECKBE-NEXT: orrs r0, r1
; CHECKBE-NEXT: vmsr p0, r0
; CHECKBE-NEXT: vpsel q1, q1, q2
diff --git a/llvm/unittests/Target/ARM/ARMSelectionDAGTest.cpp b/llvm/unittests/Target/ARM/ARMSelectionDAGTest.cpp
new file mode 100644
index 000000000000..11fa27406c53
--- /dev/null
+++ b/llvm/unittests/Target/ARM/ARMSelectionDAGTest.cpp
@@ -0,0 +1,150 @@
+//===- llvm/unittest/Target/ARM/ARMSelectionDAGTest.cpp -------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "ARMISelLowering.h"
+#include "llvm/Analysis/OptimizationRemarkEmitter.h"
+#include "llvm/AsmParser/Parser.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/Support/KnownBits.h"
+#include "llvm/Support/SourceMgr.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Target/TargetMachine.h"
+#include "gtest/gtest.h"
+
+namespace llvm {
+
+class ARMSelectionDAGTest : public testing::Test {
+protected:
+ static void SetUpTestCase() {
+ InitializeAllTargets();
+ InitializeAllTargetMCs();
+ }
+
+ void SetUp() override {
+ StringRef Assembly = "define void @f() { ret void }";
+
+ Triple TargetTriple("thumbv8.1m.main-none-eabi");
+ std::string Error;
+ const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
+ if (!T)
+ return;
+
+ TargetOptions Options;
+ TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
+ T->createTargetMachine("ARM", "", "+mve.fp", Options, None, None,
+ CodeGenOpt::Aggressive)));
+ if (!TM)
+ return;
+
+ SMDiagnostic SMError;
+ M = parseAssemblyString(Assembly, SMError, Context);
+ if (!M)
+ report_fatal_error(SMError.getMessage());
+ M->setDataLayout(TM->createDataLayout());
+
+ F = M->getFunction("f");
+ if (!F)
+ report_fatal_error("F?");
+
+ MachineModuleInfo MMI(TM.get());
+
+ MF = std::make_unique<MachineFunction>(*F, *TM, *TM->getSubtargetImpl(*F),
+ 0, MMI);
+
+ DAG = std::make_unique<SelectionDAG>(*TM, CodeGenOpt::None);
+ if (!DAG)
+ report_fatal_error("DAG?");
+ OptimizationRemarkEmitter ORE(F);
+ DAG->init(*MF, ORE, nullptr, nullptr, nullptr, nullptr, nullptr);
+ }
+
+ TargetLoweringBase::LegalizeTypeAction getTypeAction(EVT VT) {
+ return DAG->getTargetLoweringInfo().getTypeAction(Context, VT);
+ }
+
+ EVT getTypeToTransformTo(EVT VT) {
+ return DAG->getTargetLoweringInfo().getTypeToTransformTo(Context, VT);
+ }
+
+ LLVMContext Context;
+ std::unique_ptr<LLVMTargetMachine> TM;
+ std::unique_ptr<Module> M;
+ Function *F;
+ std::unique_ptr<MachineFunction> MF;
+ std::unique_ptr<SelectionDAG> DAG;
+};
+
+TEST_F(ARMSelectionDAGTest, computeKnownBits_CSINC) {
+ if (!TM)
+ return;
+ SDLoc DL;
+ SDValue Zero = DAG->getConstant(0, DL, MVT::i32);
+ SDValue One = DAG->getConstant(1, DL, MVT::i32);
+ SDValue ARMcc = DAG->getConstant(8, DL, MVT::i32);
+ SDValue Cmp = DAG->getNode(ARMISD::CMP, DL, MVT::Glue, Zero, One);
+
+ SDValue Op0 =
+ DAG->getNode(ARMISD::CSINC, DL, MVT::i32, Zero, Zero, ARMcc, Cmp);
+ KnownBits Known = DAG->computeKnownBits(Op0);
+ EXPECT_EQ(Known.Zero, 0xfffffffe);
+ EXPECT_EQ(Known.One, 0x0);
+
+ SDValue Op1 = DAG->getNode(ARMISD::CSINC, DL, MVT::i32, One, One, ARMcc, Cmp);
+ Known = DAG->computeKnownBits(Op1);
+ EXPECT_EQ(Known.Zero, 0xfffffffc);
+ EXPECT_EQ(Known.One, 0x0);
+}
+
+TEST_F(ARMSelectionDAGTest, computeKnownBits_CSINV) {
+ if (!TM)
+ return;
+ SDLoc DL;
+ SDValue Zero = DAG->getConstant(0, DL, MVT::i32);
+ SDValue One = DAG->getConstant(1, DL, MVT::i32);
+ SDValue ARMcc = DAG->getConstant(8, DL, MVT::i32);
+ SDValue Cmp = DAG->getNode(ARMISD::CMP, DL, MVT::Glue, Zero, One);
+
+ SDValue Op0 =
+ DAG->getNode(ARMISD::CSINV, DL, MVT::i32, Zero, Zero, ARMcc, Cmp);
+ KnownBits Known = DAG->computeKnownBits(Op0);
+ EXPECT_EQ(Known.Zero, 0x0);
+ EXPECT_EQ(Known.One, 0x0);
+
+ SDValue Op1 =
+ DAG->getNode(ARMISD::CSINV, DL, MVT::i32, Zero, One, ARMcc, Cmp);
+ Known = DAG->computeKnownBits(Op1);
+ EXPECT_EQ(Known.Zero, 0x1);
+ EXPECT_EQ(Known.One, 0x0);
+}
+
+TEST_F(ARMSelectionDAGTest, computeKnownBits_CSNEG) {
+ if (!TM)
+ return;
+ SDLoc DL;
+ SDValue Zero = DAG->getConstant(0, DL, MVT::i32);
+ SDValue One = DAG->getConstant(1, DL, MVT::i32);
+ SDValue ARMcc = DAG->getConstant(8, DL, MVT::i32);
+ SDValue Cmp = DAG->getNode(ARMISD::CMP, DL, MVT::Glue, Zero, One);
+
+ SDValue Op0 =
+ DAG->getNode(ARMISD::CSNEG, DL, MVT::i32, Zero, Zero, ARMcc, Cmp);
+ KnownBits Known = DAG->computeKnownBits(Op0);
+ EXPECT_EQ(Known.Zero, 0xffffffff);
+ EXPECT_EQ(Known.One, 0x0);
+
+ SDValue Op1 =
+ DAG->getNode(ARMISD::CSNEG, DL, MVT::i32, One, Zero, ARMcc, Cmp);
+ Known = DAG->computeKnownBits(Op1);
+ EXPECT_EQ(Known.Zero, 0xfffffffe);
+ EXPECT_EQ(Known.One, 0x0);
+}
+
+} // end namespace llvm
diff --git a/llvm/unittests/Target/ARM/CMakeLists.txt b/llvm/unittests/Target/ARM/CMakeLists.txt
index ba7a0449512a..7b21214e24fd 100644
--- a/llvm/unittests/Target/ARM/CMakeLists.txt
+++ b/llvm/unittests/Target/ARM/CMakeLists.txt
@@ -4,6 +4,7 @@ include_directories(
)
set(LLVM_LINK_COMPONENTS
+ ${LLVM_TARGETS_TO_BUILD}
ARMCodeGen
ARMDesc
ARMInfo
@@ -16,5 +17,6 @@ set(LLVM_LINK_COMPONENTS
)
add_llvm_target_unittest(ARMTests
+ ARMSelectionDAGTest.cpp
MachineInstrTest.cpp
)
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