[PATCH] D97188: [AArch64] Add patterns for add(udot(0, x, y), z) -> udot(z, x, y).

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:5626
+
+  def : Pat<(add (v2i32 V64:$Rd), (OpNode (v2i32 immAllZerosV), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
+            (!cast<Instruction>(NAME # "v8i8") $Rd, $Rn, $Rm)>;
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fhahn wrote:
> SjoerdMeijer wrote:
> > As you know I don't mind nice and concise little patterns, but was wondering if we don't expect this simplification to happen earlier?
> Not sure what the exact policy is, but `InstCombinerImpl::visitCallInst(` does optimize some target specific intrinsics. But I think this would  be good to have for instruction selection in any case
Oh, you mean pre-ISel? We lower a vecreduce.add(v16i8 x) to a vecreduce(udot(zero, one, x)), so this needs to be done sometime during ISel lowering at least. I'll add some tests for it.

I can make it into a DAG combine. That should capture more cases without extra patterns, and should be simple enough I think.


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  https://reviews.llvm.org/D97188/new/

https://reviews.llvm.org/D97188