[PATCH] D96492: [AVR] Add register aliases XL, YH, etc

Ben Shi via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 15 21:02:22 PST 2021


benshi001 added inline comments.


================
Comment at: llvm/lib/Target/AVR/AVRRegisterInfo.td:70
 def R25 : AVRReg<25, "r25">, DwarfRegNum<[25]>;
-def R26 : AVRReg<26, "r26">, DwarfRegNum<[26]>;
-def R27 : AVRReg<27, "r27">, DwarfRegNum<[27]>;
-def R28 : AVRReg<28, "r28">, DwarfRegNum<[28]>;
-def R29 : AVRReg<29, "r29">, DwarfRegNum<[29]>;
-def R30 : AVRReg<30, "r30">, DwarfRegNum<[30]>;
-def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>;
+def R26 : AVRReg<26, "r26", [], ["xl"]>, DwarfRegNum<[26]>;
+def R27 : AVRReg<27, "r27", [], ["xh"]>, DwarfRegNum<[27]>;
----------------
how about also add alias `__tmp_reg__` for `R0` and `__zero_reg__` for `R1` as avr-gcc does?



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96492/new/

https://reviews.llvm.org/D96492



More information about the llvm-commits mailing list