[PATCH] D96263: [RISCV] Support scalable-vector masked gather operations

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
frasercrmck added reviewers: craig.topper, evandro, rogfer01, HsiangKai.
Herald added subscribers: vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
frasercrmck requested review of this revision.
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This patch supports the masked gather intrinsics in RVV.

The RVV indexed load/store instructions only support the "unsigned
unscaled" addressing mode; indices are implicitly zero-extended or
truncated to XLEN and are treated as byte offsets. This ISA supports the
intrinsics directly, but not the majority of various forms of the
MGATHER SDNode that LLVM combines to. Any signed or scaled indexing is
extended to the XLEN value type and scaled accordingly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96263

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

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