[PATCH] D92112: [Hexagon] Add support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added a reviewer: kparzysz.
Herald added subscribers: steven.zhang, hiraditya.
Herald added a project: LLVM.
RKSimon requested review of this revision.

This should handle the basic integer min/max handling, I may have missed something wrt Hexagon type legalization semantics (for instance it sets add/sub etc to be legal for v4i8/v2i16 types but I couldn't get it to work for min/max).

I haven't been able to get the HVX equivalents to work either - any tips would appreciated.

This is some necessary cleanup work for min/max ops to eventually help us move the add/sub sat patterns into DAGCombine - D91876 <https://reviews.llvm.org/D91876>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92112

Files:
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonPatterns.td
  llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D92112.307644.patch
Type: text/x-patch
Size: 8901 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201125/271ebc8c/attachment.bin>