[PATCH] D89447: [MachineInstr] Add support for instructions with multiple memory operands.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Has the SystremZ Prefetch issues been resolved?



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Comment at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1733
+  /// in MachineInstr returns conservative result to avoid quadratic overhead.
+  virtual unsigned getMemOperandAACheckLimit() const { return 4; }
+
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So the limit on the number of alias checks is effectively 16?

Would it be worth making it so limit is on the total number of checks, not the MemOperands per instruction? That way an instruction with a single operand could be compared to an instruction with many (which I imagine would be a common case).


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Comment at: llvm/lib/CodeGen/MachineInstr.cpp:1292
+    // Assume `MayAlias` if any memory operand is not unordered one.
+    if (!MMOa->isUnordered() || !MMOb->isUnordered())
       return true;
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Why is this new ordered check needed? I didn't think that atomics had multiple memory operands.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D89447/new/

https://reviews.llvm.org/D89447