[PATCH] D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added a comment.

In D90024#2350657 <https://reviews.llvm.org/D90024#2350657>, @dmgreen wrote:

> I'm happy with that explanation, and would be happy with this patch going ahead. The mir test above seems to show it failing before and working now.

Exactly:

  llc: /home/andrea/llvm-project/llvm/include/llvm/CodeGen/MachineOperand.h:536: int64_t llvm::MachineOperand::getImm() const: Assertion `isImm() && "Wrong MachineOperand accessor"' failed.

It looks like that predicate has always been wrong.
Sorry for causing panic :-P (I guess, better safe than sorry).


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