[PATCH] D90029: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate

Andrea Di Biagio via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Oct 23 07:22:32 PDT 2020

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andreadb added a comment.

The new predicate looks good to me.


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  https://reviews.llvm.org/D90029/new/

https://reviews.llvm.org/D90029

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