[PATCH] D89576: [SVE][CodeGen] Lower scalable masked scatters

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

In D89576#2343049 <https://reviews.llvm.org/D89576#2343049>, @craig.topper wrote:

> I was thinking of vXi8 and vXi16 vectors that can't be used as indices on X86.

If `vXi8` and `vXi16` are not legal, the type-legaliser will re-add sign/zero extends when doing type-promotion in `DAGTypeLegalizer::PromoteIntOp_MSCATTER`, for which it uses the signedness of the `MemIndexType`. The same is also needed for SVE, which only supports nxvXi32 and nxvXi64 indices. But at least this ensures that e.g. a zero-extend of a legal nxv4i32 -> illegal nxv4i64 will get encoded as legal `UNSIGNED_[UN]SCALED nxv4i32` for which the architecture will generate the instruction with zero-extending index. Do you think that will be sufficient?


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