[PATCH] D89777: [TableGen][SchedModels] Fix read/write variant substitution
Eugene Leviant via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 22 08:18:27 PDT 2020
evgeny777 added inline comments.
================
Comment at: llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s:2287
# CHECK-NEXT: - - - - 1.00 - - - smladxhi r2, r3, r5, r8
-# CHECK-NEXT: - - - - 2.00 - - - smlal r2, r3, r5, r8
-# CHECK-NEXT: - - - - 2.00 - - - smlals r2, r3, r5, r8
-# CHECK-NEXT: - - - - 2.00 - - - smlaleq r2, r3, r5, r8
-# CHECK-NEXT: - - - - 2.00 - - - smlalshi r2, r3, r5, r8
-# CHECK-NEXT: - - - - 2.00 - - - smlalbb r3, r1, r9, r0
-# CHECK-NEXT: - - - - 2.00 - - - smlalbt r5, r6, r4, r1
-# CHECK-NEXT: - - - - 2.00 - - - smlaltb r4, r2, r3, r2
-# CHECK-NEXT: - - - - 2.00 - - - smlaltt r8, r3, r8, r4
-# CHECK-NEXT: - - - - 2.00 - - - smlalbbge r3, r1, r9, r0
-# CHECK-NEXT: - - - - 2.00 - - - smlalbtle r5, r6, r4, r1
-# CHECK-NEXT: - - - - 2.00 - - - smlaltbne r4, r2, r3, r2
-# CHECK-NEXT: - - - - 2.00 - - - smlaltteq r8, r3, r8, r4
-# CHECK-NEXT: - - - - 2.00 - - - smlald r2, r3, r5, r8
+# CHECK-NEXT: - - - 2.00 - - - - smlal r2, r3, r5, r8
+# CHECK-NEXT: - 1.00 1.00 - 2.00 - - - smlals r2, r3, r5, r8
----------------
dmgreen wrote:
> dmgreen wrote:
> > These now use L somehow? Am I reading that right?
> Oh. Is A57Write_4cyc_1M incorrectly specified?
```
def A57Write_4cyc_1M : SchedWriteRes<[A57UnitL]> { let Latency = 4; }
```
Likely.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D89777/new/
https://reviews.llvm.org/D89777
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