[PATCH] D89195: [PowerPC][Power10] Exploit store rightmost vector element instructions.

[Lei Huang via Phabricator via llvm-commits]

lei added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll:1
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
----------------
There's some redundancies here:
1. The default CHECK are not used in any of the run lines, but are updated in some cases.
2. The newly generated CHECK-LE and CHECK-BE are at times exact duplicate of each other and of the default CHECK.

Suggest to update thus so it's more clear what the changes are:
 ```
RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN:   FileCheck %s --check-prefix=CHECK,LE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN:   FileCheck %s --check-prefix=CHECK,BE
```
For cases where there is a differnce in LE and BE behaviour, remove the default CHECK and add new.  Otherwise just leave the original default CHECKs.


================
Comment at: llvm/test/CodeGen/PowerPC/store-rightmost-vector-elt.ll:4
+; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
+; RUN:     < %s | FileCheck %s
+
----------------
run line for BE?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89195/new/

https://reviews.llvm.org/D89195