[llvm] 5e73162 - [NFC][MC] Use [MC]Register in MachineVerifier
Mircea Trofin via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 20 20:42:47 PDT 2020
Author: Mircea Trofin
Date: 2020-10-20T20:42:35-07:00
New Revision: 5e731625f3d641296d972c30da4018a9be78f3fe
URL: https://github.com/llvm/llvm-project/commit/5e731625f3d641296d972c30da4018a9be78f3fe
DIFF: https://github.com/llvm/llvm-project/commit/5e731625f3d641296d972c30da4018a9be78f3fe.diff
LOG: [NFC][MC] Use [MC]Register in MachineVerifier
Differential Revision: https://reviews.llvm.org/D89815
Added:
Modified:
llvm/lib/CodeGen/MachineVerifier.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index cf48d292d932..dc25146d7868 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -102,10 +102,10 @@ namespace {
bool isFunctionRegBankSelected;
bool isFunctionSelected;
- using RegVector = SmallVector<unsigned, 16>;
+ using RegVector = SmallVector<Register, 16>;
using RegMaskVector = SmallVector<const uint32_t *, 4>;
- using RegSet = DenseSet<unsigned>;
- using RegMap = DenseMap<unsigned, const MachineInstr *>;
+ using RegSet = DenseSet<Register>;
+ using RegMap = DenseMap<Register, const MachineInstr *>;
using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
const MachineInstr *FirstNonPHI;
@@ -120,10 +120,10 @@ namespace {
SlotIndex lastIndex;
// Add Reg and any sub-registers to RV
- void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
+ void addRegWithSubRegs(RegVector &RV, Register Reg) {
RV.push_back(Reg);
- if (Register::isPhysicalRegister(Reg))
- for (const MCPhysReg &SubReg : TRI->subregs(Reg))
+ if (Reg.isPhysical())
+ for (const MCPhysReg &SubReg : TRI->subregs(Reg.asMCReg()))
RV.push_back(SubReg);
}
@@ -159,8 +159,8 @@ namespace {
// Add register to vregsRequired if it belongs there. Return true if
// anything changed.
- bool addRequired(unsigned Reg) {
- if (!Register::isVirtualRegister(Reg))
+ bool addRequired(Register Reg) {
+ if (!Reg.isVirtual())
return false;
if (regsLiveOut.count(Reg))
return false;
@@ -170,7 +170,7 @@ namespace {
// Same for a full set.
bool addRequired(const RegSet &RS) {
bool Changed = false;
- for (unsigned Reg : RS)
+ for (Register Reg : RS)
Changed |= addRequired(Reg);
return Changed;
}
@@ -184,7 +184,7 @@ namespace {
}
// Live-out registers are either in regsLiveOut or vregsPassed.
- bool isLiveOut(unsigned Reg) const {
+ bool isLiveOut(Register Reg) const {
return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
}
};
@@ -192,13 +192,13 @@ namespace {
// Extra register info per MBB.
DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
- bool isReserved(unsigned Reg) {
- return Reg < regsReserved.size() && regsReserved.test(Reg);
+ bool isReserved(Register Reg) {
+ return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
}
- bool isAllocatable(unsigned Reg) const {
- return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
- !regsReserved.test(Reg);
+ bool isAllocatable(Register Reg) const {
+ return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
+ !regsReserved.test(Reg.id());
}
// Analysis information if available
@@ -226,7 +226,7 @@ namespace {
LLT MOVRegType = LLT{});
void report_context(const LiveInterval &LI) const;
- void report_context(const LiveRange &LR, unsigned VRegUnit,
+ void report_context(const LiveRange &LR, Register VRegUnit,
LaneBitmask LaneMask) const;
void report_context(const LiveRange::Segment &S) const;
void report_context(const VNInfo &VNI) const;
@@ -234,18 +234,19 @@ namespace {
void report_context(MCPhysReg PhysReg) const;
void report_context_liverange(const LiveRange &LR) const;
void report_context_lanemask(LaneBitmask LaneMask) const;
- void report_context_vreg(unsigned VReg) const;
- void report_context_vreg_regunit(unsigned VRegOrUnit) const;
+ void report_context_vreg(Register VReg) const;
+ void report_context_vreg_regunit(Register VRegOrUnit) const;
void verifyInlineAsm(const MachineInstr *MI);
void checkLiveness(const MachineOperand *MO, unsigned MONum);
void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
- SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
+ SlotIndex UseIdx, const LiveRange &LR,
+ Register VRegOrUnit,
LaneBitmask LaneMask = LaneBitmask::getNone());
void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
- SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
- bool SubRangeCheck = false,
+ SlotIndex DefIdx, const LiveRange &LR,
+ Register VRegOrUnit, bool SubRangeCheck = false,
LaneBitmask LaneMask = LaneBitmask::getNone());
void markReachable(const MachineBasicBlock *MBB);
@@ -256,12 +257,12 @@ namespace {
void verifyLiveVariables();
void verifyLiveIntervals();
void verifyLiveInterval(const LiveInterval&);
- void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
+ void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
LaneBitmask);
- void verifyLiveRangeSegment(const LiveRange&,
- const LiveRange::const_iterator I, unsigned,
+ void verifyLiveRangeSegment(const LiveRange &,
+ const LiveRange::const_iterator I, Register,
LaneBitmask);
- void verifyLiveRange(const LiveRange&, unsigned,
+ void verifyLiveRange(const LiveRange &, Register,
LaneBitmask LaneMask = LaneBitmask::getNone());
void verifyStackFrame();
@@ -508,7 +509,7 @@ void MachineVerifier::report_context(const LiveInterval &LI) const {
errs() << "- interval: " << LI << '\n';
}
-void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
+void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
LaneBitmask LaneMask) const {
report_context_liverange(LR);
report_context_vreg_regunit(VRegUnit);
@@ -532,11 +533,11 @@ void MachineVerifier::report_context(MCPhysReg PReg) const {
errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
}
-void MachineVerifier::report_context_vreg(unsigned VReg) const {
+void MachineVerifier::report_context_vreg(Register VReg) const {
errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
}
-void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
+void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
if (Register::isVirtualRegister(VRegOrUnit)) {
report_context_vreg(VRegOrUnit);
} else {
@@ -1958,8 +1959,10 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
- unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
- LaneBitmask LaneMask) {
+ unsigned MONum, SlotIndex UseIdx,
+ const LiveRange &LR,
+ Register VRegOrUnit,
+ LaneBitmask LaneMask) {
LiveQueryResult LRQ = LR.Query(UseIdx);
// Check if we have a segment at the use, note however that we only need one
// live subregister range, the others may be dead.
@@ -1980,8 +1983,11 @@ void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
}
void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
- unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
- bool SubRangeCheck, LaneBitmask LaneMask) {
+ unsigned MONum, SlotIndex DefIdx,
+ const LiveRange &LR,
+ Register VRegOrUnit,
+ bool SubRangeCheck,
+ LaneBitmask LaneMask) {
if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
assert(VNI && "NULL valno is not allowed");
if (VNI->def != DefIdx) {
@@ -2025,7 +2031,7 @@ void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
const MachineInstr *MI = MO->getParent();
- const unsigned Reg = MO->getReg();
+ const Register Reg = MO->getReg();
// Both use and def operands can read a register.
if (MO->readsReg()) {
@@ -2043,8 +2049,9 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
// Check the cached regunit intervals.
- if (Register::isPhysicalRegister(Reg) && !isReserved(Reg)) {
- for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
+ if (Reg.isPhysical() && !isReserved(Reg)) {
+ for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
+ ++Units) {
if (MRI->isReservedRegUnit(*Units))
continue;
if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
@@ -2190,9 +2197,9 @@ void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
// Kill any masked registers.
while (!regMasks.empty()) {
const uint32_t *Mask = regMasks.pop_back_val();
- for (unsigned Reg : regsLive)
- if (Register::isPhysicalRegister(Reg) &&
- MachineOperand::clobbersPhysReg(Mask, Reg))
+ for (Register Reg : regsLive)
+ if (Reg.isPhysical() &&
+ MachineOperand::clobbersPhysReg(Mask, Reg.asMCReg()))
regsDead.push_back(Reg);
}
set_subtract(regsLive, regsDead); regsDead.clear();
@@ -2225,7 +2232,7 @@ struct VRegFilter {
// Add elements to the filter itself. \pre Input set \p FromRegSet must have
// no duplicates. Both virtual and physical registers are fine.
template <typename RegSetT> void add(const RegSetT &FromRegSet) {
- SmallVector<unsigned, 0> VRegsBuffer;
+ SmallVector<Register, 0> VRegsBuffer;
filterAndAdd(FromRegSet, VRegsBuffer);
}
// Filter \p FromRegSet through the filter and append passed elements into \p
@@ -2233,13 +2240,13 @@ struct VRegFilter {
// \returns true if anything changed.
template <typename RegSetT>
bool filterAndAdd(const RegSetT &FromRegSet,
- SmallVectorImpl<unsigned> &ToVRegs) {
+ SmallVectorImpl<Register> &ToVRegs) {
unsigned SparseUniverse = Sparse.size();
unsigned NewSparseUniverse = SparseUniverse;
unsigned NewDenseSize = Dense.size();
size_t Begin = ToVRegs.size();
- for (unsigned Reg : FromRegSet) {
- if (!Register::isVirtualRegister(Reg))
+ for (Register Reg : FromRegSet) {
+ if (!Reg.isVirtual())
continue;
unsigned Index = Register::virtReg2Index(Reg);
if (Index < SparseUniverseMax) {
@@ -2263,7 +2270,7 @@ struct VRegFilter {
Sparse.resize(NewSparseUniverse);
Dense.reserve(NewDenseSize);
for (unsigned I = Begin; I < End; ++I) {
- unsigned Reg = ToVRegs[I];
+ Register Reg = ToVRegs[I];
unsigned Index = Register::virtReg2Index(Reg);
if (Index < SparseUniverseMax)
Sparse.set(Index);
@@ -2296,7 +2303,7 @@ struct VRegFilter {
// universe). filter_b implicitly contains all physical registers at all times.
class FilteringVRegSet {
VRegFilter Filter;
- SmallVector<unsigned, 0> VRegs;
+ SmallVector<Register, 0> VRegs;
public:
// Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
@@ -2474,7 +2481,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
// Check for killed virtual registers that should be live out.
for (const auto &MBB : *MF) {
BBInfo &MInfo = MBBInfoMap[&MBB];
- for (unsigned VReg : MInfo.vregsRequired)
+ for (Register VReg : MInfo.vregsRequired)
if (MInfo.regsKilled.count(VReg)) {
report("Virtual register killed in block, but needed live out.", &MBB);
errs() << "Virtual register " << printReg(VReg)
@@ -2484,7 +2491,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
if (!MF->empty()) {
BBInfo &MInfo = MBBInfoMap[&MF->front()];
- for (unsigned VReg : MInfo.vregsRequired) {
+ for (Register VReg : MInfo.vregsRequired) {
report("Virtual register defs don't dominate all uses.", MF);
report_context_vreg(VReg);
}
@@ -2543,8 +2550,8 @@ void MachineVerifier::visitMachineFunctionAfter() {
void MachineVerifier::verifyLiveVariables() {
assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
- for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
- unsigned Reg = Register::index2VirtReg(i);
+ for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
for (const auto &MBB : *MF) {
BBInfo &MInfo = MBBInfoMap[&MBB];
@@ -2569,8 +2576,8 @@ void MachineVerifier::verifyLiveVariables() {
void MachineVerifier::verifyLiveIntervals() {
assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
- for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
- unsigned Reg = Register::index2VirtReg(i);
+ for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
// Spilling and splitting may leave unused registers around. Skip them.
if (MRI->reg_nodbg_empty(Reg))
@@ -2594,7 +2601,7 @@ void MachineVerifier::verifyLiveIntervals() {
}
void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
- const VNInfo *VNI, unsigned Reg,
+ const VNInfo *VNI, Register Reg,
LaneBitmask LaneMask) {
if (VNI->isUnused())
return;
@@ -2687,8 +2694,8 @@ void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
const LiveRange::const_iterator I,
- unsigned Reg, LaneBitmask LaneMask)
-{
+ Register Reg,
+ LaneBitmask LaneMask) {
const LiveRange::Segment &S = *I;
const VNInfo *VNI = S.valno;
assert(VNI && "Live segment has no valno");
@@ -2899,7 +2906,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
}
}
-void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
+void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
LaneBitmask LaneMask) {
for (const VNInfo *VNI : LR.valnos)
verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
@@ -2909,7 +2916,7 @@ void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
}
void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
- unsigned Reg = LI.reg();
+ Register Reg = LI.reg();
assert(Register::isVirtualRegister(Reg));
verifyLiveRange(LI, Reg);
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