[PATCH] D89382: [SVE][CodeGen] Lower scalable integer vector reductions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:3936-3937
   case ISD::SMIN:
+    if (Op.getValueType().getVectorElementType() == MVT::i1)
+      return DAG.getNode(ISD::OR, SDLoc(Op), Op.getValueType(),
+                         Op.getOperand(0), Op.getOperand(1));
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On reflection and since you're going the extra mile, I'd rather have this transformation (and the matching reduction ones) at the `SelectionDAG::getNode()` level so that we can just force a canonical representation for all targets as early as possible and then it'll never be a concern from a legalisation point of view.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89382/new/

https://reviews.llvm.org/D89382