[PATCH] D89822: [ARM] [TableGen] Clean up !if(!eq(boolean, 1) and related booleans

[Paul C. Anagnostopoulos via Phabricator via llvm-commits]

Paul-C-Anagnostopoulos created this revision.
Paul-C-Anagnostopoulos added reviewers: lattner, nhaehnle, rengolin, t.p.northover.
Herald added subscribers: llvm-commits, danielkiss, dmgreen, hiraditya, kristof.beyls.
Herald added a project: LLVM.
Paul-C-Anagnostopoulos requested review of this revision.

With the addition of the !not operator to TableGen, I'm making a pass over all the targets to clean up the boolean expressions. This is the patch for the ARM.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D89822

Files:
  llvm/lib/Target/ARM/ARMInstrMVE.td


Index: llvm/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -2474,7 +2474,7 @@
 
   let Predicates = [HasMVEInt] in {
     // VQABS and VQNEG have more difficult isel patterns defined elsewhere
-    if !eq(saturate, 0) then {
+    if !not(saturate) then {
       def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$v))),
                 (VTI.Vec (Inst $v))>;
     }
@@ -4777,7 +4777,7 @@
   let Inst{16} = 0b1;
   let Inst{12} = T;
   let Inst{8} = 0b0;
-  let Inst{7} = !if(!eq(bit_17, 0), 1, 0);
+  let Inst{7} = !not(bit_17);
   let Inst{0} = 0b1;
   let validForTailPredication = 1;
   let retainsPreviousHalfElement = 1;
@@ -4808,7 +4808,7 @@
                                (VTI.Vec MQPR:$Qm), (i32 top))),
             (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec MQPR:$Qm)))>;
 
-  if !eq(top, 0) then {
+  if !not(top) then {
     // If we see MVEvmovn(a,ARMvrev(b),1), that wants to overwrite the odd
     // lanes of a with the odd lanes of b. In other words, the lanes we're
     // _keeping_ from a are the even ones. So we can flip it round and say that


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