[PATCH] D89777: [TableGen][SchedModels] Fix read/write variant substitution

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 created this revision.
evgeny777 added reviewers: SjoerdMeijer, javed.absar, dmgreen, andreadb.
Herald added subscribers: gbedwell, hiraditya.
Herald added a project: LLVM.
evgeny777 requested review of this revision.

ATM, this doesn't work:

  // Model1.td
  let SchedModel = Model1 in {
     def Model1ReadMAC64Lo : SchedReadVariant<...>;
     def : SchedAlias<ReadMac64Lo, Model1ReadMAC64Lo>;
  }

  // Model2.td
  let SchedModel = Model2 in {
     def Model2WriteMAC64Lo : SchedWriteVariant<...>;
     def : SchedAlias<WriteMac64Lo, Model2WriteMAC64Lo>;
  }

Trying to compile this will result in TableGen error, because TableGen fails to process case when:
a) Sched class has both read and write variants
b) Read and write variants reside in different processor models

I've changed `WriteMAC64Lo` in cortex-a57 model in order to test this. According to optimization guide multiply long operations, which set flags, should take 1 cycle longer and have additional integer uop.


https://reviews.llvm.org/D89777

Files:
  llvm/lib/Target/ARM/ARMScheduleA57.td
  llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
  llvm/utils/TableGen/CodeGenSchedule.cpp

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