[PATCH] D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir:16
+  {
+    ret void
+  }
----------------
rogfer01 wrote:
> frasercrmck wrote:
> > Is this test function missing a body? I can't see how it would generate the expected MIR
> This test checks the case when the `vl` is not `RISCV::X0` by using the vreg `%3`. 
> 
> We can't currently express this in LLVM but we still need some LLVM IR function. Perhaps we can add some comment explaining this.
Okay yeah I see my original misunderstanding; sorry about that. Presumably there will eventually be intrinsics that can set `vl`; I've seen those in other proposals. Until then, a comment wouldn't hurt. 


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  https://reviews.llvm.org/D89449/new/

https://reviews.llvm.org/D89449