[llvm] 6bb60d3 - [VE] Add setcc for fp128
Kazushi Marukawa via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 19 05:37:05 PDT 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-10-19T21:36:57+09:00
New Revision: 6bb60d3e26808bd9189d94ee4abeb768263ca269
URL: https://github.com/llvm/llvm-project/commit/6bb60d3e26808bd9189d94ee4abeb768263ca269
DIFF: https://github.com/llvm/llvm-project/commit/6bb60d3e26808bd9189d94ee4abeb768263ca269.diff
LOG: [VE] Add setcc for fp128
Add setcc for fp128 and clean existing ISel patterns. Also add
a regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D89683
Added:
llvm/test/CodeGen/VE/setcc.ll
Modified:
llvm/lib/Target/VE/VEInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
index 4eee79aca9fe..65dbb68ce176 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -1788,47 +1788,27 @@ def GETSTACKTOP : Pseudo<(outs I64:$dst), (ins),
// or %res, 0, (0)1 ; initialize by 0
// CMOV %res, (63)0, %tmp ; set 1 if %tmp is true
-def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCSIOp:$cond)),
- (EXTRACT_SUBREG
- (CMOVLrm (icond2cc $cond),
- (CMPSLrr i64:$LHS, i64:$RHS),
- !add(63, 64),
- (ORim 0, 0)), sub_i32)>;
-
-def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCUIOp:$cond)),
- (EXTRACT_SUBREG
- (CMOVLrm (icond2cc $cond),
- (CMPULrr i64:$LHS, i64:$RHS),
- !add(63, 64),
- (ORim 0, 0)), sub_i32)>;
-
-def : Pat<(i32 (setcc i32:$LHS, i32:$RHS, CCSIOp:$cond)),
- (EXTRACT_SUBREG
- (CMOVWrm (icond2cc $cond),
- (CMPSWSXrr i32:$LHS, i32:$RHS),
- !add(63, 64),
- (ORim 0, 0)), sub_i32)>;
-
-def : Pat<(i32 (setcc i32:$LHS, i32:$RHS, CCUIOp:$cond)),
- (EXTRACT_SUBREG
- (CMOVWrm (icond2cc $cond),
- (CMPUWrr i32:$LHS, i32:$RHS),
- !add(63, 64),
- (ORim 0, 0)), sub_i32)>;
-
-def : Pat<(i32 (setcc f64:$LHS, f64:$RHS, cond:$cond)),
- (EXTRACT_SUBREG
- (CMOVDrm (fcond2cc $cond),
- (FCMPDrr f64:$LHS, f64:$RHS),
- !add(63, 64),
- (ORim 0, 0)), sub_i32)>;
-
-def : Pat<(i32 (setcc f32:$LHS, f32:$RHS, cond:$cond)),
- (EXTRACT_SUBREG
- (CMOVSrm (fcond2cc $cond),
- (FCMPSrr f32:$LHS, f32:$RHS),
- !add(63, 64),
- (ORim 0, 0)), sub_i32)>;
+class setccrr<Instruction INSN> :
+ OutPatFrag<(ops node:$cond, node:$comp),
+ (EXTRACT_SUBREG
+ (INSN $cond, $comp,
+ !add(63, 64), // means (63)0 == 1
+ (ORim 0, 0)), sub_i32)>;
+
+def : Pat<(i32 (setcc i32:$l, i32:$r, CCSIOp:$cond)),
+ (setccrr<CMOVWrm> (icond2cc $cond), (CMPSWSXrr $l, $r))>;
+def : Pat<(i32 (setcc i32:$l, i32:$r, CCUIOp:$cond)),
+ (setccrr<CMOVWrm> (icond2cc $cond), (CMPUWrr $l, $r))>;
+def : Pat<(i32 (setcc i64:$l, i64:$r, CCSIOp:$cond)),
+ (setccrr<CMOVLrm> (icond2cc $cond), (CMPSLrr $l, $r))>;
+def : Pat<(i32 (setcc i64:$l, i64:$r, CCUIOp:$cond)),
+ (setccrr<CMOVLrm> (icond2cc $cond), (CMPULrr $l, $r))>;
+def : Pat<(i32 (setcc f32:$l, f32:$r, cond:$cond)),
+ (setccrr<CMOVSrm> (fcond2cc $cond), (FCMPSrr $l, $r))>;
+def : Pat<(i32 (setcc f64:$l, f64:$r, cond:$cond)),
+ (setccrr<CMOVDrm> (fcond2cc $cond), (FCMPDrr $l, $r))>;
+def : Pat<(i32 (setcc f128:$l, f128:$r, cond:$cond)),
+ (setccrr<CMOVDrm> (fcond2cc $cond), (FCMPQrr $l, $r))>;
// Special SELECTCC pattern matches
// Use min/max for better performance.
diff --git a/llvm/test/CodeGen/VE/setcc.ll b/llvm/test/CodeGen/VE/setcc.ll
new file mode 100644
index 000000000000..5dd66647c9f8
--- /dev/null
+++ b/llvm/test/CodeGen/VE/setcc.ll
@@ -0,0 +1,193 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+;;; Test all combination of input type and output type among following types.
+;;;
+;;; Types:
+;;; i1/i8/u8/i16/u16/i32/u32/i64/u64/i128/u128/float/double/fp128
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_i1(i1 zeroext %0, i1 zeroext %1) {
+; CHECK-LABEL: setcc_i1:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: xor %s0, %s0, %s1
+; CHECK-NEXT: xor %s0, 1, %s0
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = xor i1 %0, %1
+ %4 = xor i1 %3, true
+ ret i1 %4
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_i8(i8 signext %0, i8 signext %1) {
+; CHECK-LABEL: setcc_i8:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i8 %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_u8(i8 zeroext %0, i8 zeroext %1) {
+; CHECK-LABEL: setcc_u8:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i8 %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_i16(i16 signext %0, i16 signext %1) {
+; CHECK-LABEL: setcc_i16:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i16 %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_u16(i16 zeroext %0, i16 zeroext %1) {
+; CHECK-LABEL: setcc_u16:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i16 %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_i32(i32 signext %0, i32 signext %1) {
+; CHECK-LABEL: setcc_i32:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i32 %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_u32(i32 zeroext %0, i32 zeroext %1) {
+; CHECK-LABEL: setcc_u32:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i32 %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_i64(i64 %0, i64 %1) {
+; CHECK-LABEL: setcc_i64:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i64 %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_u64(i64 %0, i64 %1) {
+; CHECK-LABEL: setcc_u64:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i64 %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_i128(i128 %0, i128 %1) {
+; CHECK-LABEL: setcc_i128:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: xor %s1, %s1, %s3
+; CHECK-NEXT: xor %s0, %s0, %s2
+; CHECK-NEXT: or %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i128 %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_u128(i128 %0, i128 %1) {
+; CHECK-LABEL: setcc_u128:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: xor %s1, %s1, %s3
+; CHECK-NEXT: xor %s0, %s0, %s2
+; CHECK-NEXT: or %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i128 %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_float(float %0, float %1) {
+; CHECK-LABEL: setcc_float:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = fcmp fast oeq float %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_double(double %0, double %1) {
+; CHECK-LABEL: setcc_double:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = fcmp fast oeq double %0, %1
+ ret i1 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_quad(fp128 %0, fp128 %1) {
+; CHECK-LABEL: setcc_quad:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: fcmp.q %s0, %s0, %s2
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = fcmp fast oeq fp128 %0, %1
+ ret i1 %3
+}
More information about the llvm-commits
mailing list