[PATCH] D89553: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate (alternative approach)

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb accepted this revision.
andreadb added a comment.
This revision is now accepted and ready to land.

LGTM.

The patch is mostly a mechanical change (i.e. a lot of boilerplate to introduce a new scheduling predicate).

@dmgreen has already verified in D89458 <https://reviews.llvm.org/D89458> that the ARM changes in the mca test are good.



================
Comment at: llvm/lib/MC/MCSchedule.cpp:77
   while (SCDesc->isVariant()) {
-    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
+    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID);
     SCDesc = getSchedClassDesc(SchedClass);
----------------
not sure if this is more than 80-cols.


================
Comment at: llvm/lib/MC/MCSchedule.cpp:123
   while (SCDesc->isVariant()) {
-    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
+    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID);
     SCDesc = getSchedClassDesc(SchedClass);
----------------
same.


================
Comment at: llvm/tools/llvm-mca/Views/InstructionInfoView.cpp:106
     while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
-      SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &Inst, CPUID);
+      SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &Inst, &MCII, CPUID);
 
----------------
80-col


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89553/new/

https://reviews.llvm.org/D89553