[llvm] c2551c1 - [GlobalISel] Remove scalar src from non-sequential fadd/fmul reductions.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2020-10-15T15:51:44-07:00
New Revision: c2551c1f4058d2c3cc4964b1d1d0ca5946036f6c

URL: https://github.com/llvm/llvm-project/commit/c2551c1f4058d2c3cc4964b1d1d0ca5946036f6c
DIFF: https://github.com/llvm/llvm-project/commit/c2551c1f4058d2c3cc4964b1d1d0ca5946036f6c.diff

LOG: [GlobalISel] Remove scalar src from non-sequential fadd/fmul reductions.

It's probably better to split these into separate G_FADD/G_FMUL + G_VECREDUCE
operations in the translator rather than carrying the scalar around. The
majority of the time it'll get simplified away as the scalars are probably
identity values.

Differential Revision: https://reviews.llvm.org/D89150

Added: 
    

Modified: 
    llvm/include/llvm/Target/GenericOpcodes.td
    llvm/lib/CodeGen/MachineVerifier.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    llvm/test/MachineVerifier/test_vector_reductions.mir

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 3693632ed643..4cda6a8c511d 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1265,35 +1265,26 @@ def G_SHUFFLE_VECTOR: GenericInstruction {
 // Vector reductions
 //------------------------------------------------------------------------------
 
-def G_VECREDUCE_SEQ_FADD : GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type1:$acc, type2:$v);
-  let hasSideEffects = 0;
-}
-
-def G_VECREDUCE_SEQ_FMUL : GenericInstruction {
+class VectorReduction : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type1:$acc, type2:$v);
+  let InOperandList = (ins type1:$v);
   let hasSideEffects = 0;
 }
 
-def G_VECREDUCE_FADD : GenericInstruction {
+def G_VECREDUCE_SEQ_FADD : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$acc, type2:$v);
   let hasSideEffects = 0;
 }
 
-def G_VECREDUCE_FMUL : GenericInstruction {
+def G_VECREDUCE_SEQ_FMUL : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$acc, type2:$v);
   let hasSideEffects = 0;
 }
 
-class VectorReduction : GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type1:$v);
-  let hasSideEffects = 0;
-}
+def G_VECREDUCE_FADD : VectorReduction;
+def G_VECREDUCE_FMUL : VectorReduction;
 
 def G_VECREDUCE_FMAX : VectorReduction;
 def G_VECREDUCE_FMIN : VectorReduction;

diff  --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 5c22673d5e1e..cf48d292d932 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1489,20 +1489,20 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
     break;
   }
   case TargetOpcode::G_VECREDUCE_SEQ_FADD:
-  case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
-  case TargetOpcode::G_VECREDUCE_FADD:
-  case TargetOpcode::G_VECREDUCE_FMUL: {
+  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
     LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
     if (!DstTy.isScalar())
       report("Vector reduction requires a scalar destination type", MI);
     if (!Src1Ty.isScalar())
-      report("FADD/FMUL vector reduction requires a scalar 1st operand", MI);
+      report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
     if (!Src2Ty.isVector())
-      report("FADD/FMUL vector reduction must have a vector 2nd operand", MI);
+      report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
     break;
   }
+  case TargetOpcode::G_VECREDUCE_FADD:
+  case TargetOpcode::G_VECREDUCE_FMUL:
   case TargetOpcode::G_VECREDUCE_FMAX:
   case TargetOpcode::G_VECREDUCE_FMIN:
   case TargetOpcode::G_VECREDUCE_ADD:

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index ad8964718c76..303610da9423 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -619,10 +619,10 @@
 # DEBUG-NEXT: G_VECREDUCE_SEQ_FMUL (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: G_VECREDUCE_FADD (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
+# DEBUG-NEXT: G_VECREDUCE_FADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: G_VECREDUCE_FMUL (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
+# DEBUG-NEXT: G_VECREDUCE_FMUL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_VECREDUCE_FMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices

diff  --git a/llvm/test/MachineVerifier/test_vector_reductions.mir b/llvm/test/MachineVerifier/test_vector_reductions.mir
index c11e0b3c9493..d66d1ed05519 100644
--- a/llvm/test/MachineVerifier/test_vector_reductions.mir
+++ b/llvm/test/MachineVerifier/test_vector_reductions.mir
@@ -25,10 +25,10 @@ body:             |
     ; CHECK: Bad machine code: Vector reduction requires a scalar destination type
 
     %dst:_(s64) = G_VECREDUCE_SEQ_FADD %vec_v2s64, %vec_v2s64
-    ; CHECK: Bad machine code: FADD/FMUL vector reduction requires a scalar 1st operand
+    ; CHECK: Bad machine code: Sequential FADD/FMUL vector reduction requires a scalar 1st operand
 
     %dst:_(s64) = G_VECREDUCE_SEQ_FADD %scalar_s64, %scalar_s64
-    ; CHECK: Bad machine code: FADD/FMUL vector reduction must have a vector 2nd operand
+    ; CHECK: Bad machine code: Sequential FADD/FMUL vector reduction must have a vector 2nd operand
 
     %dst2:_(s64) = G_VECREDUCE_MUL %scalar_s64
     ; CHECK: Bad machine code: Vector reduction requires vector source