[PATCH] D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension

[Evandro Menezes via Phabricator via llvm-commits]

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The companion RFC gives lots of details on the overall strategy, but we summarize it here:

- LLVM IR involving vector types is going to be selected using pseudo instructions (only `MachineInstr`).  These pseudo instructions contain dummy operands to represent the vector type being operated and the vector length for the operation.

- These two dummy operands, as set by instruction selection, will be used by the custom inserter to prepend every operation with an appropriate `vsetvli` instruction that ensures the vector architecture is properly configured for the operation.  Not in this patch: later passes will remove the redundant `vsetvli` instructions.

- Register classes of tuples of vector registers are used to represent vector register groups (LMUL > 1).

- Those pseudos are eventually lowered into the actual instructions when emitting the `MCInst`s.

About the patch:

Because there is a bit of initial infrastructure required, this is the minimal patch that allows us to select instructions for 3 LLVM IR instructions: load, add and store vectors of integers.  LLVM IR operations have "whole-vector" semantics (as in they generate values for all the elements).

Later patches will extend the information represented in TableGen.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>


https://reviews.llvm.org/D89449

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoPseudoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll
  llvm/utils/TableGen/GlobalISelEmitter.cpp

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