[llvm] b3a38bc - [AMDGPU] Correct typos in SIMemoryLegalizer.cpp comments

[via llvm-commits]

Author: Tony
Date: 2020-10-15T02:07:56Z
New Revision: b3a38bc2dcab478e9f1a7e96029393a19cd9357d

URL: https://github.com/llvm/llvm-project/commit/b3a38bc2dcab478e9f1a7e96029393a19cd9357d
DIFF: https://github.com/llvm/llvm-project/commit/b3a38bc2dcab478e9f1a7e96029393a19cd9357d.diff

LOG: [AMDGPU] Correct typos in SIMemoryLegalizer.cpp comments

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index c03709194917..5786b317ea01 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -716,7 +716,7 @@ bool SIGfx6CacheControl::enableLoadCacheBypass(
   /// sequentially consistent, and no other thread can access scratch
   /// memory.
 
-  /// Other address spaces do not hava a cache.
+  /// Other address spaces do not have a cache.
 
   return Changed;
 }
@@ -770,7 +770,7 @@ bool SIGfx6CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,
   /// sequentially consistent, and no other thread can access scratch
   /// memory.
 
-  /// Other address spaces do not hava a cache.
+  /// Other address spaces do not have a cache.
 
   if (Pos == Position::AFTER)
     --MI;
@@ -972,7 +972,7 @@ bool SIGfx10CacheControl::enableLoadCacheBypass(
   /// sequentially consistent, and no other thread can access scratch
   /// memory.
 
-  /// Other address spaces do not hava a cache.
+  /// Other address spaces do not have a cache.
 
   return Changed;
 }
@@ -1035,7 +1035,7 @@ bool SIGfx10CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,
   /// sequentially consistent, and no other thread can access scratch
   /// memory.
 
-  /// Other address spaces do not hava a cache.
+  /// Other address spaces do not have a cache.
 
   if (Pos == Position::AFTER)
     --MI;