[PATCH] D89399: [AMDGPU] Set rsrc1 flags for graphics shaders

Wed Oct 14 16:25:36 PDT 2020

nhaehnle added inline comments.

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Comment at: llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp:1245-1252
     MD->setRsrc1(CC, S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
-        S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks));
+                         S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks) |
+                         S_00B848_PRIORITY(CurrentProgramInfo.Priority) |
+                         S_00B848_FLOAT_MODE(CurrentProgramInfo.FloatMode) |
+                         S_00B848_PRIV(CurrentProgramInfo.Priv) |
+                         S_00B848_DX10_CLAMP(CurrentProgramInfo.DX10Clamp) |
+                         S_00B848_DEBUG_MODE(CurrentProgramInfo.DebugMode) |
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All shader types have MEM_ORDERED, and GS and HS also have WGP_MODE.

Annoyingly, the bits aren't always in the same place.

What I would suggest is:
- Remove SIProgramInfo::ComputePGMRsrc1 because it's fully redundant
- Add a getPgmRsrc1 helper function which computes the correct register value based on the calling convention

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89399/new/

https://reviews.llvm.org/D89399