[EXTERNAL] [PATCH] D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant

[Evgeny Leviant via llvm-commits]

Hey Simon,



Should be fixed in 836d0addee4a2ce07d09d68484823221cbb062b7



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From: Simon Pilgrim via Phabricator<mailto:reviews at reviews.llvm.org>
Sent: 13 октября 2020 г. 14:13
To: Evgeny Leviant<mailto:eleviant at accesssoftek.com>; atrick at apple.com<mailto:atrick at apple.com>; javeda at graphcore.ai<mailto:javeda at graphcore.ai>; craig.topper at gmail.com<mailto:craig.topper at gmail.com>; andrea.dibiagio at gmail.com<mailto:andrea.dibiagio at gmail.com>; david.green at arm.com<mailto:david.green at arm.com>; sjoerd.meijer at arm.com<mailto:sjoerd.meijer at arm.com>
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Subject: [EXTERNAL] [PATCH] D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant



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RKSimon added inline comments.


================
Comment at: llvm/utils/TableGen/CodeGenSchedule.cpp:1679
+                  [&FromSC](unsigned PIdx) {
+                    return !FromSC.InstRWProcIndices.count(PIdx);
+                  });
----------------
@evgeny777 I'm seeing some asserts on msvc builds inside the count() on ARMGenSubtargetInfo.inc generation


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89114/new/

https://reviews.llvm.org/D89114

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