[PATCH] D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

LGTM. Cheers



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Comment at: llvm/test/TableGen/sched-aliases.td:47
+
+def ProcFoo0 : SubtargetFeature<"foo-0", "ARMProcFamily", "foo-0",
+                                "Test Processor #1", []>;
----------------
evgeny777 wrote:
> dmgreen wrote:
> > Is ProcFoo0 needed?
> Yes. TableGen won't add model which is not bound to any processor
Sure, but is the subtarget feature needed? I'm pretty sure you can remove this ProcFoo0 and have the features for "foo-0-model" empty.


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Comment at: llvm/test/tools/llvm-mca/ARM/A57-sxtb.s:2
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=armv7 -mcpu=cortex-a57 -instruction-tables < %s | FileCheck %s
+
----------------
evgeny777 wrote:
> dmgreen wrote:
> > armv7 -> armv8
> > 
> > Is this file generated with the script? I would expect more tables at the bottom.
> > 
> > Can you pre-commit the file and show the differences here.
> I've reduced test case to make it easier reviewing it.
> Pre-commit seems good idea. See 7102793065f2329a2fde78f32a1f2582dd89b0e7
Thanks. Like it


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  https://reviews.llvm.org/D89114/new/

https://reviews.llvm.org/D89114