[llvm] a324d8f - [AArch64] Add tests for 128-bit shift variations.
Eli Friedman via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 12 14:51:54 PDT 2020
Author: Eli Friedman
Date: 2020-10-12T14:48:58-07:00
New Revision: a324d8f964bf421fa7d8b882b0f64ead28c4149c
URL: https://github.com/llvm/llvm-project/commit/a324d8f964bf421fa7d8b882b0f64ead28c4149c
DIFF: https://github.com/llvm/llvm-project/commit/a324d8f964bf421fa7d8b882b0f64ead28c4149c.diff
LOG: [AArch64] Add tests for 128-bit shift variations.
It looks like there's still some room for optimization; the funnel shift
lowering is more efficient than the lowering of actual shifts.
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-long-shift.ll
llvm/test/CodeGen/AArch64/funnel-shift.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-long-shift.ll b/llvm/test/CodeGen/AArch64/arm64-long-shift.ll
index 39436d6dd34d..a3588c306aa3 100644
--- a/llvm/test/CodeGen/AArch64/arm64-long-shift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-long-shift.ll
@@ -1,58 +1,108 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck %s
define i128 @shl(i128 %r, i128 %s) nounwind readnone {
; CHECK-LABEL: shl:
-; CHECK: neg [[REV_SHIFT:x[0-9]+]], x2
-; CHECK: lsr [[LO_FOR_HI_NORMAL:x[0-9]+]], x0, [[REV_SHIFT]]
-; CHECK: cmp x2, #0
-; CHECK: csel [[LO_FOR_HI:x[0-9]+]], xzr, [[LO_FOR_HI_NORMAL]], eq
-; CHECK: lsl [[HI_FOR_HI:x[0-9]+]], x1, x2
-; CHECK: orr [[HI_NORMAL:x[0-9]+]], [[LO_FOR_HI]], [[HI_FOR_HI]]
-; CHECK: lsl [[HI_BIG_SHIFT:x[0-9]+]], x0, x2
-; CHECK: sub [[EXTRA_SHIFT:x[0-9]+]], x2, #64
-; CHECK: cmp [[EXTRA_SHIFT]], #0
-; CHECK: csel x1, [[HI_BIG_SHIFT]], [[HI_NORMAL]], ge
-; CHECK: csel x0, xzr, [[HI_BIG_SHIFT]], ge
-; CHECK: ret
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg x8, x2
+; CHECK-NEXT: lsr x8, x0, x8
+; CHECK-NEXT: cmp x2, #0 // =0
+; CHECK-NEXT: csel x8, xzr, x8, eq
+; CHECK-NEXT: lsl x9, x1, x2
+; CHECK-NEXT: orr x8, x8, x9
+; CHECK-NEXT: lsl x9, x0, x2
+; CHECK-NEXT: sub x10, x2, #64 // =64
+; CHECK-NEXT: cmp x10, #0 // =0
+; CHECK-NEXT: csel x1, x9, x8, ge
+; CHECK-NEXT: csel x0, xzr, x9, ge
+; CHECK-NEXT: ret
%shl = shl i128 %r, %s
ret i128 %shl
}
+define i128 @shl_mask(i128 %r, i128 %s) nounwind readnone {
+; CHECK-LABEL: shl_mask:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsl x8, x1, x2
+; CHECK-NEXT: lsr x9, x0, #1
+; CHECK-NEXT: and x10, x2, #0x3f
+; CHECK-NEXT: eor x10, x10, #0x3f
+; CHECK-NEXT: lsr x9, x9, x10
+; CHECK-NEXT: orr x1, x8, x9
+; CHECK-NEXT: lsl x0, x0, x2
+; CHECK-NEXT: ret
+ %mask = and i128 %s, 63
+ %shl = shl i128 %r, %mask
+ ret i128 %shl
+}
+
define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
; CHECK-LABEL: ashr:
-; CHECK: neg [[REV_SHIFT:x[0-9]+]], x2
-; CHECK: lsl [[HI_FOR_LO_NORMAL:x[0-9]+]], x1, [[REV_SHIFT]]
-; CHECK: cmp x2, #0
-; CHECK: csel [[HI_FOR_LO:x[0-9]+]], xzr, [[HI_FOR_LO_NORMAL]], eq
-; CHECK: lsr [[LO_FOR_LO:x[0-9]+]], x0, x2
-; CHECK: orr [[LO_NORMAL:x[0-9]+]], [[LO_FOR_LO]], [[HI_FOR_LO]]
-; CHECK: asr [[LO_BIG_SHIFT:x[0-9]+]], x1, x2
-; CHECK: sub [[EXTRA_SHIFT:x[0-9]+]], x2, #64
-; CHECK: cmp [[EXTRA_SHIFT]], #0
-; CHECK: csel x0, [[LO_BIG_SHIFT]], [[LO_NORMAL]], ge
-; CHECK: asr [[BIGSHIFT_HI:x[0-9]+]], x1, #63
-; CHECK: csel x1, [[BIGSHIFT_HI]], [[LO_BIG_SHIFT]], ge
-; CHECK: ret
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg x8, x2
+; CHECK-NEXT: lsl x8, x1, x8
+; CHECK-NEXT: cmp x2, #0 // =0
+; CHECK-NEXT: csel x8, xzr, x8, eq
+; CHECK-NEXT: lsr x9, x0, x2
+; CHECK-NEXT: orr x8, x9, x8
+; CHECK-NEXT: asr x9, x1, x2
+; CHECK-NEXT: sub x10, x2, #64 // =64
+; CHECK-NEXT: cmp x10, #0 // =0
+; CHECK-NEXT: csel x0, x9, x8, ge
+; CHECK-NEXT: asr x8, x1, #63
+; CHECK-NEXT: csel x1, x8, x9, ge
+; CHECK-NEXT: ret
%shr = ashr i128 %r, %s
ret i128 %shr
}
+define i128 @ashr_mask(i128 %r, i128 %s) nounwind readnone {
+; CHECK-LABEL: ashr_mask:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsr x8, x0, x2
+; CHECK-NEXT: lsl x9, x1, #1
+; CHECK-NEXT: and x10, x2, #0x3f
+; CHECK-NEXT: eor x10, x10, #0x3f
+; CHECK-NEXT: lsl x9, x9, x10
+; CHECK-NEXT: orr x0, x8, x9
+; CHECK-NEXT: asr x1, x1, x2
+; CHECK-NEXT: ret
+ %mask = and i128 %s, 63
+ %shr = ashr i128 %r, %mask
+ ret i128 %shr
+}
+
define i128 @lshr(i128 %r, i128 %s) nounwind readnone {
; CHECK-LABEL: lshr:
-; CHECK: neg [[REV_SHIFT:x[0-9]+]], x2
-; CHECK: lsl [[HI_FOR_LO_NORMAL:x[0-9]+]], x1, [[REV_SHIFT]]
-; CHECK: cmp x2, #0
-; CHECK: csel [[HI_FOR_LO:x[0-9]+]], xzr, [[HI_FOR_LO_NORMAL]], eq
-; CHECK: lsr [[LO_FOR_LO:x[0-9]+]], x0, x2
-; CHECK: orr [[LO_NORMAL:x[0-9]+]], [[LO_FOR_LO]], [[HI_FOR_LO]]
-; CHECK: lsr [[LO_BIG_SHIFT:x[0-9]+]], x1, x2
-; CHECK: cmp [[EXTRA_SHIFT]], #0
-; CHECK: csel x0, [[LO_BIG_SHIFT]], [[LO_NORMAL]], ge
-; CHECK: csel x1, xzr, [[LO_BIG_SHIFT]], ge
-; CHECK: ret
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg x8, x2
+; CHECK-NEXT: lsl x8, x1, x8
+; CHECK-NEXT: cmp x2, #0 // =0
+; CHECK-NEXT: csel x8, xzr, x8, eq
+; CHECK-NEXT: lsr x9, x0, x2
+; CHECK-NEXT: orr x8, x9, x8
+; CHECK-NEXT: lsr x9, x1, x2
+; CHECK-NEXT: sub x10, x2, #64 // =64
+; CHECK-NEXT: cmp x10, #0 // =0
+; CHECK-NEXT: csel x0, x9, x8, ge
+; CHECK-NEXT: csel x1, xzr, x9, ge
+; CHECK-NEXT: ret
%shr = lshr i128 %r, %s
ret i128 %shr
}
+
+define i128 @lshr_mask(i128 %r, i128 %s) nounwind readnone {
+; CHECK-LABEL: lshr_mask:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsr x8, x0, x2
+; CHECK-NEXT: lsl x9, x1, #1
+; CHECK-NEXT: and x10, x2, #0x3f
+; CHECK-NEXT: eor x10, x10, #0x3f
+; CHECK-NEXT: lsl x9, x9, x10
+; CHECK-NEXT: orr x0, x8, x9
+; CHECK-NEXT: lsr x1, x1, x2
+; CHECK-NEXT: ret
+ %mask = and i128 %s, 63
+ %shr = lshr i128 %r, %mask
+ ret i128 %shr
+}
diff --git a/llvm/test/CodeGen/AArch64/funnel-shift.ll b/llvm/test/CodeGen/AArch64/funnel-shift.ll
index 011cbf476c38..18a192084fdf 100644
--- a/llvm/test/CodeGen/AArch64/funnel-shift.ll
+++ b/llvm/test/CodeGen/AArch64/funnel-shift.ll
@@ -29,6 +29,19 @@ define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
ret i32 %f
}
+define i64 @fshl_i64(i64 %x, i64 %y, i64 %z) {
+; CHECK-LABEL: fshl_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mvn w9, w2
+; CHECK-NEXT: lsr x10, x1, #1
+; CHECK-NEXT: lsl x8, x0, x2
+; CHECK-NEXT: lsr x9, x10, x9
+; CHECK-NEXT: orr x0, x8, x9
+; CHECK-NEXT: ret
+ %f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 %z)
+ ret i64 %f
+}
+
; Verify that weird types are minimally supported.
declare i37 @llvm.fshl.i37(i37, i37, i37)
define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
@@ -153,6 +166,19 @@ define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
ret i32 %f
}
+define i64 @fshr_i64(i64 %x, i64 %y, i64 %z) {
+; CHECK-LABEL: fshr_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mvn w9, w2
+; CHECK-NEXT: lsl x10, x0, #1
+; CHECK-NEXT: lsr x8, x1, x2
+; CHECK-NEXT: lsl x9, x10, x9
+; CHECK-NEXT: orr x0, x9, x8
+; CHECK-NEXT: ret
+ %f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 %z)
+ ret i64 %f
+}
+
; Verify that weird types are minimally supported.
declare i37 @llvm.fshr.i37(i37, i37, i37)
define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
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