[PATCH] D89183: [VE] Add vector load/store instructions

[Simon Moll via Phabricator via llvm-commits]

simoll added inline comments.


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Comment at: llvm/lib/Target/VE/VEISelLowering.cpp:637-672
+  addRegisterClass(MVT::v2i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v4i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v8i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v16i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v32i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v64i32, &VE::V64RegClass);
+  addRegisterClass(MVT::v128i32, &VE::V64RegClass);
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I wonder why there are vector types that do not map directly to vector registers.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D89183/new/

https://reviews.llvm.org/D89183