[PATCH] D88974: [SVE] Lower fixed length VECREDUCE_XOR operation

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally created this revision.
cameron.mcinally added reviewers: paulwalker-arm, dancgr, kmclaughlin, efriedma.
Herald added subscribers: llvm-commits, psnobl, hiraditya, tschuett.
Herald added a project: LLVM.
cameron.mcinally requested review of this revision.

Pretty much a direct copy of VECREDUCE_OR, except that I added a setOperationAction(,..) loop for the unsupported NEON bitwise reductions. Thoughts on that?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D88974

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll

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