[llvm] 333b2ab - [SVE] Lower fixed length VECREDUCE_OR operation
Cameron McInally via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 7 07:56:36 PDT 2020
Author: Cameron McInally
Date: 2020-10-07T09:56:25-05:00
New Revision: 333b2ab60b61afb342a8d271477849fb445a26af
URL: https://github.com/llvm/llvm-project/commit/333b2ab60b61afb342a8d271477849fb445a26af
DIFF: https://github.com/llvm/llvm-project/commit/333b2ab60b61afb342a8d271477849fb445a26af.diff
LOG: [SVE] Lower fixed length VECREDUCE_OR operation
Differential Revision: https://reviews.llvm.org/D88847
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 308628a7f834..c2972ab4f2f7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1121,6 +1121,13 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::VECREDUCE_AND, MVT::v2i32, Custom);
setOperationAction(ISD::VECREDUCE_AND, MVT::v4i32, Custom);
setOperationAction(ISD::VECREDUCE_AND, MVT::v2i64, Custom);
+ setOperationAction(ISD::VECREDUCE_OR, MVT::v8i8, Custom);
+ setOperationAction(ISD::VECREDUCE_OR, MVT::v16i8, Custom);
+ setOperationAction(ISD::VECREDUCE_OR, MVT::v4i16, Custom);
+ setOperationAction(ISD::VECREDUCE_OR, MVT::v8i16, Custom);
+ setOperationAction(ISD::VECREDUCE_OR, MVT::v2i32, Custom);
+ setOperationAction(ISD::VECREDUCE_OR, MVT::v4i32, Custom);
+ setOperationAction(ISD::VECREDUCE_OR, MVT::v2i64, Custom);
setOperationAction(ISD::VECREDUCE_SMAX, MVT::v2i64, Custom);
setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom);
setOperationAction(ISD::VECREDUCE_UMAX, MVT::v2i64, Custom);
@@ -1263,6 +1270,7 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
@@ -3944,6 +3952,7 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
return LowerSTORE(Op, DAG);
case ISD::VECREDUCE_ADD:
case ISD::VECREDUCE_AND:
+ case ISD::VECREDUCE_OR:
case ISD::VECREDUCE_SMAX:
case ISD::VECREDUCE_SMIN:
case ISD::VECREDUCE_UMAX:
@@ -9732,6 +9741,7 @@ SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
// Try to lower fixed length reductions to SVE.
EVT SrcVT = Src.getValueType();
bool OverrideNEON = Op.getOpcode() == ISD::VECREDUCE_AND ||
+ Op.getOpcode() == ISD::VECREDUCE_OR ||
(Op.getOpcode() != ISD::VECREDUCE_ADD &&
SrcVT.getVectorElementType() == MVT::i64);
if (useSVEForFixedLengthVectorVT(SrcVT, OverrideNEON)) {
@@ -9740,6 +9750,8 @@ SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
return LowerFixedLengthReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG);
case ISD::VECREDUCE_AND:
return LowerFixedLengthReductionToSVE(AArch64ISD::ANDV_PRED, Op, DAG);
+ case ISD::VECREDUCE_OR:
+ return LowerFixedLengthReductionToSVE(AArch64ISD::ORV_PRED, Op, DAG);
case ISD::VECREDUCE_SMAX:
return LowerFixedLengthReductionToSVE(AArch64ISD::SMAXV_PRED, Op, DAG);
case ISD::VECREDUCE_SMIN:
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
index b95564cbc1e5..efab691b4a9f 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
@@ -343,6 +343,329 @@ define i64 @andv_v32i64(<32 x i64>* %a) #0 {
ret i64 %res
}
+;
+; ORV
+;
+
+; No single instruction NEON ORV support. Use SVE.
+define i8 @orv_v8i8(<8 x i8> %a) #0 {
+; CHECK-LABEL: orv_v8i8:
+; CHECK: ptrue [[PG:p[0-9]+]].b, vl8
+; CHECK: orv b[[REDUCE:[0-9]+]], [[PG]], z0.b
+; CHECK: fmov w0, s[[REDUCE]]
+; CHECK: ret
+ %res = call i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8> %a)
+ ret i8 %res
+}
+
+; No single instruction NEON ORV support. Use SVE.
+define i8 @orv_v16i8(<16 x i8> %a) #0 {
+; CHECK-LABEL: orv_v16i8:
+; CHECK: ptrue [[PG:p[0-9]+]].b, vl16
+; CHECK: orv b[[REDUCE:[0-9]+]], [[PG]], z0.b
+; CHECK: fmov w0, s[[REDUCE]]
+; CHECK: ret
+ %res = call i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8> %a)
+ ret i8 %res
+}
+
+define i8 @orv_v32i8(<32 x i8>* %a) #0 {
+; CHECK-LABEL: orv_v32i8:
+; VBITS_GE_256: ptrue [[PG:p[0-9]+]].b, vl32
+; VBITS_GE_256-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_GE_256-NEXT: orv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
+; VBITS_GE_256-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_256-NEXT: ret
+ %op = load <32 x i8>, <32 x i8>* %a
+ %res = call i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8> %op)
+ ret i8 %res
+}
+
+define i8 @orv_v64i8(<64 x i8>* %a) #0 {
+; CHECK-LABEL: orv_v64i8:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].b, vl64
+; VBITS_GE_512-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: orv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
+; VBITS_GE_512-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32
+; VBITS_EQ_256-DAG: mov w[[A_HI:[0-9]+]], #32
+; VBITS_EQ_256-DAG: ld1b { [[LO:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1b { [[HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A_HI]]]
+; VBITS_EQ_256-DAG: orr [[OR:z[0-9]+]].d, [[LO]].d, [[HI]].d
+; VBITS_EQ_256-DAG: orv b[[REDUCE:[0-9]+]], [[PG]], [[OR]].b
+; VBITS_EQ_256-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_EQ_256-NEXT: ret
+
+ %op = load <64 x i8>, <64 x i8>* %a
+ %res = call i8 @llvm.experimental.vector.reduce.or.v64i8(<64 x i8> %op)
+ ret i8 %res
+}
+
+define i8 @orv_v128i8(<128 x i8>* %a) #0 {
+; CHECK-LABEL: orv_v128i8:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].b, vl128
+; VBITS_GE_1024-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: orv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
+; VBITS_GE_1024-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_1024-NEXT: ret
+ %op = load <128 x i8>, <128 x i8>* %a
+ %res = call i8 @llvm.experimental.vector.reduce.or.v128i8(<128 x i8> %op)
+ ret i8 %res
+}
+
+define i8 @orv_v256i8(<256 x i8>* %a) #0 {
+; CHECK-LABEL: orv_v256i8:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].b, vl256
+; VBITS_GE_2048-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: orv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
+; VBITS_GE_2048-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_2048-NEXT: ret
+ %op = load <256 x i8>, <256 x i8>* %a
+ %res = call i8 @llvm.experimental.vector.reduce.or.v256i8(<256 x i8> %op)
+ ret i8 %res
+}
+
+; No single instruction NEON ORV support. Use SVE.
+define i16 @orv_v4i16(<4 x i16> %a) #0 {
+; CHECK-LABEL: orv_v4i16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl4
+; CHECK: orv h[[REDUCE:[0-9]+]], [[PG]], z0.h
+; CHECK: fmov w0, s[[REDUCE]]
+; CHECK: ret
+ %res = call i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16> %a)
+ ret i16 %res
+}
+
+; No single instruction NEON ORV support. Use SVE.
+define i16 @orv_v8i16(<8 x i16> %a) #0 {
+; CHECK-LABEL: orv_v8i16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl8
+; CHECK: orv h[[REDUCE:[0-9]+]], [[PG]], z0.h
+; CHECK: fmov w0, s[[REDUCE]]
+; CHECK: ret
+ %res = call i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16> %a)
+ ret i16 %res
+}
+
+define i16 @orv_v16i16(<16 x i16>* %a) #0 {
+; CHECK-LABEL: orv_v16i16:
+; VBITS_GE_256: ptrue [[PG:p[0-9]+]].h, vl16
+; VBITS_GE_256-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_256-NEXT: orv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
+; VBITS_GE_256-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_256-NEXT: ret
+ %op = load <16 x i16>, <16 x i16>* %a
+ %res = call i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16> %op)
+ ret i16 %res
+}
+
+define i16 @orv_v32i16(<32 x i16>* %a) #0 {
+; CHECK-LABEL: orv_v32i16:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32
+; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: orv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
+; VBITS_GE_512-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1h { [[LO:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1h { [[HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: orr [[OR:z[0-9]+]].d, [[LO]].d, [[HI]].d
+; VBITS_EQ_256-DAG: orv h[[REDUCE:[0-9]+]], [[PG]], [[OR]].h
+; VBITS_EQ_256-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_EQ_256-NEXT: ret
+ %op = load <32 x i16>, <32 x i16>* %a
+ %res = call i16 @llvm.experimental.vector.reduce.or.v32i16(<32 x i16> %op)
+ ret i16 %res
+}
+
+define i16 @orv_v64i16(<64 x i16>* %a) #0 {
+; CHECK-LABEL: orv_v64i16:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64
+; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: orv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
+; VBITS_GE_1024-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_1024-NEXT: ret
+ %op = load <64 x i16>, <64 x i16>* %a
+ %res = call i16 @llvm.experimental.vector.reduce.or.v64i16(<64 x i16> %op)
+ ret i16 %res
+}
+
+define i16 @orv_v128i16(<128 x i16>* %a) #0 {
+; CHECK-LABEL: orv_v128i16:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128
+; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: orv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
+; VBITS_GE_2048-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_2048-NEXT: ret
+ %op = load <128 x i16>, <128 x i16>* %a
+ %res = call i16 @llvm.experimental.vector.reduce.or.v128i16(<128 x i16> %op)
+ ret i16 %res
+}
+
+; No single instruction NEON ORV support. Use SVE.
+define i32 @orv_v2i32(<2 x i32> %a) #0 {
+; CHECK-LABEL: orv_v2i32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl2
+; CHECK: orv [[REDUCE:s[0-9]+]], [[PG]], z0.s
+; CHECK: fmov w0, [[REDUCE]]
+; CHECK: ret
+ %res = call i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32> %a)
+ ret i32 %res
+}
+
+; No single instruction NEON ORV support. Use SVE.
+define i32 @orv_v4i32(<4 x i32> %a) #0 {
+; CHECK-LABEL: orv_v4i32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl4
+; CHECK: orv [[REDUCE:s[0-9]+]], [[PG]], z0.s
+; CHECK: fmov w0, [[REDUCE]]
+; CHECK: ret
+ %res = call i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a)
+ ret i32 %res
+}
+
+define i32 @orv_v8i32(<8 x i32>* %a) #0 {
+; CHECK-LABEL: orv_v8i32:
+; VBITS_GE_256: ptrue [[PG:p[0-9]+]].s, vl8
+; VBITS_GE_256-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_256-NEXT: orv [[REDUCE:s[0-9]+]], [[PG]], [[OP]].s
+; VBITS_GE_256-NEXT: fmov w0, [[REDUCE]]
+; VBITS_GE_256-NEXT: ret
+ %op = load <8 x i32>, <8 x i32>* %a
+ %res = call i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32> %op)
+ ret i32 %res
+}
+
+define i32 @orv_v16i32(<16 x i32>* %a) #0 {
+; CHECK-LABEL: orv_v16i32:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16
+; VBITS_GE_512-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: orv [[REDUCE:s[0-9]+]], [[PG]], [[OP]].s
+; VBITS_GE_512-NEXT: fmov w0, [[REDUCE]]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1w { [[LO:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1w { [[HI:z[0-9]+]].s }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: orr [[OR:z[0-9]+]].d, [[LO]].d, [[HI]].d
+; VBITS_EQ_256-DAG: orv [[REDUCE:s[0-9]+]], [[PG]], [[OR]].s
+; VBITS_EQ_256-NEXT: fmov w0, [[REDUCE]]
+; VBITS_EQ_256-NEXT: ret
+ %op = load <16 x i32>, <16 x i32>* %a
+ %res = call i32 @llvm.experimental.vector.reduce.or.v16i32(<16 x i32> %op)
+ ret i32 %res
+}
+
+define i32 @orv_v32i32(<32 x i32>* %a) #0 {
+; CHECK-LABEL: orv_v32i32:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32
+; VBITS_GE_1024-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: orv [[REDUCE:s[0-9]+]], [[PG]], [[OP]].s
+; VBITS_GE_1024-NEXT: fmov w0, [[REDUCE]]
+; VBITS_GE_1024-NEXT: ret
+ %op = load <32 x i32>, <32 x i32>* %a
+ %res = call i32 @llvm.experimental.vector.reduce.or.v32i32(<32 x i32> %op)
+ ret i32 %res
+}
+
+define i32 @orv_v64i32(<64 x i32>* %a) #0 {
+; CHECK-LABEL: orv_v64i32:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64
+; VBITS_GE_2048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: orv [[REDUCE:s[0-9]+]], [[PG]], [[OP]].s
+; VBITS_GE_2048-NEXT: fmov w0, [[REDUCE]]
+; VBITS_GE_2048-NEXT: ret
+ %op = load <64 x i32>, <64 x i32>* %a
+ %res = call i32 @llvm.experimental.vector.reduce.or.v64i32(<64 x i32> %op)
+ ret i32 %res
+}
+
+; Nothing to do for single element vectors.
+define i64 @orv_v1i64(<1 x i64> %a) #0 {
+; CHECK-LABEL: orv_v1i64:
+; CHECK: fmov x0, d0
+; CHECK: ret
+ %res = call i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64> %a)
+ ret i64 %res
+}
+
+; Use SVE for 128-bit vectors
+define i64 @orv_v2i64(<2 x i64> %a) #0 {
+; CHECK-LABEL: orv_v2i64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl2
+; CHECK: orv [[REDUCE:d[0-9]+]], [[PG]], z0.d
+; CHECK: fmov x0, [[REDUCE]]
+; CHECK: ret
+ %res = call i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64> %a)
+ ret i64 %res
+}
+
+define i64 @orv_v4i64(<4 x i64>* %a) #0 {
+; CHECK-LABEL: orv_v4i64:
+; VBITS_GE_256: ptrue [[PG:p[0-9]+]].d, vl4
+; VBITS_GE_256-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_256-NEXT: orv [[REDUCE:d[0-9]+]], [[PG]], [[OP]].d
+; VBITS_GE_256-NEXT: fmov x0, [[REDUCE]]
+; VBITS_GE_256-NEXT: ret
+ %op = load <4 x i64>, <4 x i64>* %a
+ %res = call i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64> %op)
+ ret i64 %res
+}
+
+define i64 @orv_v8i64(<8 x i64>* %a) #0 {
+; CHECK-LABEL: orv_v8i64:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8
+; VBITS_GE_512-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: orv [[REDUCE:d[0-9]+]], [[PG]], [[OP]].d
+; VBITS_GE_512-NEXT: fmov x0, [[REDUCE]]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1d { [[LO:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1d { [[HI:z[0-9]+]].d }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: orr [[OR:z[0-9]+]].d, [[LO]].d, [[HI]].d
+; VBITS_EQ_256-DAG: orv [[REDUCE:d[0-9]+]], [[PG]], [[OR]].d
+; VBITS_EQ_256-NEXT: fmov x0, [[REDUCE]]
+; VBITS_EQ_256-NEXT: ret
+ %op = load <8 x i64>, <8 x i64>* %a
+ %res = call i64 @llvm.experimental.vector.reduce.or.v8i64(<8 x i64> %op)
+ ret i64 %res
+}
+
+define i64 @orv_v16i64(<16 x i64>* %a) #0 {
+; CHECK-LABEL: orv_v16i64:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16
+; VBITS_GE_1024-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: orv [[REDUCE:d[0-9]+]], [[PG]], [[OP]].d
+; VBITS_GE_1024-NEXT: fmov x0, [[REDUCE]]
+; VBITS_GE_1024-NEXT: ret
+ %op = load <16 x i64>, <16 x i64>* %a
+ %res = call i64 @llvm.experimental.vector.reduce.or.v16i64(<16 x i64> %op)
+ ret i64 %res
+}
+
+define i64 @orv_v32i64(<32 x i64>* %a) #0 {
+; CHECK-LABEL: orv_v32i64:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32
+; VBITS_GE_2048-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: orv [[REDUCE:d[0-9]+]], [[PG]], [[OP]].d
+; VBITS_GE_2048-NEXT: fmov x0, [[REDUCE]]
+; VBITS_GE_2048-NEXT: ret
+ %op = load <32 x i64>, <32 x i64>* %a
+ %res = call i64 @llvm.experimental.vector.reduce.or.v32i64(<32 x i64> %op)
+ ret i64 %res
+}
+
attributes #0 = { "target-features"="+sve" }
declare i8 @llvm.experimental.vector.reduce.and.v8i8(<8 x i8>)
@@ -372,3 +695,31 @@ declare i64 @llvm.experimental.vector.reduce.and.v4i64(<4 x i64>)
declare i64 @llvm.experimental.vector.reduce.and.v8i64(<8 x i64>)
declare i64 @llvm.experimental.vector.reduce.and.v16i64(<16 x i64>)
declare i64 @llvm.experimental.vector.reduce.and.v32i64(<32 x i64>)
+
+declare i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8>)
+declare i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8>)
+declare i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8>)
+declare i8 @llvm.experimental.vector.reduce.or.v64i8(<64 x i8>)
+declare i8 @llvm.experimental.vector.reduce.or.v128i8(<128 x i8>)
+declare i8 @llvm.experimental.vector.reduce.or.v256i8(<256 x i8>)
+
+declare i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16>)
+declare i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16>)
+declare i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16>)
+declare i16 @llvm.experimental.vector.reduce.or.v32i16(<32 x i16>)
+declare i16 @llvm.experimental.vector.reduce.or.v64i16(<64 x i16>)
+declare i16 @llvm.experimental.vector.reduce.or.v128i16(<128 x i16>)
+
+declare i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32>)
+declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32>)
+declare i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32>)
+declare i32 @llvm.experimental.vector.reduce.or.v16i32(<16 x i32>)
+declare i32 @llvm.experimental.vector.reduce.or.v32i32(<32 x i32>)
+declare i32 @llvm.experimental.vector.reduce.or.v64i32(<64 x i32>)
+
+declare i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64>)
+declare i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64>)
+declare i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64>)
+declare i64 @llvm.experimental.vector.reduce.or.v8i64(<8 x i64>)
+declare i64 @llvm.experimental.vector.reduce.or.v16i64(<16 x i64>)
+declare i64 @llvm.experimental.vector.reduce.or.v32i64(<32 x i64>)
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