[PATCH] D88742: [AArch64] Identify SAD pattern for v16i8 type

Wed Oct 7 03:27:00 PDT 2020

mivnay added a comment.

In D88742#2316222 <https://reviews.llvm.org/D88742#2316222>, @dmgreen wrote:

> In D88742#2314735 <https://reviews.llvm.org/D88742#2314735>, @mivnay wrote:
>
>>> What part of sadb are you worried about? I thought they could be treated the same, given you are extended from enough extra bits. But I may be mistaken, they can be somewhat difficult.
>>
>> I am worried about the semantics of sabd instruction especially about `v16i32 (sub(sext(v16i8), sext(v16i8))) to v16i32 sext(sub(v16i8, v16i8))` part. Can this be looked at later once my other patches are through?
>
> The return type of the abd is positive unsigned, so I think if turning it into `v16i32 zext(sabd(v16i8, v16i8))` should be valid? But it's worth testing that, I may be mistaken..

I am not sure about the validity either and need to test it. Can that be added as enhancement later and go ahead with the current pattern?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88742/new/

https://reviews.llvm.org/D88742