[PATCH] D88759: [RISCV] Add SiFive cores to the CPU option

[Evandro Menezes via Phabricator via llvm-commits]

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Add the SiFive cores E76 and U74 using the SiFive 7 series microarchitecture.


https://reviews.llvm.org/D88759

Files:
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td

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