[PATCH] D88201: [DAGCombiner] Add decomposition patterns for Mul-by-Imm.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:16061
+    int64_t Imm = ConstNode->getSExtValue();
+    unsigned Shift = countTrailingZeros<uint64_t>(Imm);
+    Imm >>= Shift;
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Just to confirm: no target besides PPC is going to see any diffs from this patch because they don't check the constant for trailing zeros yet?

(We really should implement the `TODO` from the DAGCombiner code comment, so every target doesn't have to duplicate this logic.)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88201/new/

https://reviews.llvm.org/D88201