[PATCH] D88707: [SVE] Lower fixed length VECREDUCE_AND operation

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally created this revision.
cameron.mcinally added reviewers: paulwalker-arm, kmclaughlin, dancgr, efriedma.
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Some things to consider:

1. NEON currently lowers the 64-bit and 128-bit vector AND reductions to a tree based algorithm, IINM. Do we want to go with the NEON lowerings or SVE instructions for those? The i8 and i16 cases should probably use SVE for code clarity. But the v2 vectors may be short enough that NEON is a win. They'll expand to something like:

  ext v1.16b, v0.16b, v0.16b, #8
  and v0.8b, v0.8b, v1.8b

Are we okay with tuning these later? Or should I do a study now?

2. If we choose SVE instructions for #1, the OverrideNEON flag is getting bulky again. We might want to consider refactoring that, since we'll need to add more cases for OR and XOR.

3. I named the new test file `sve-fixed-length-log-reduce.ll`. The `log` follows the existing AND tests in /AArch64, but is a little misleading since they're bitwise operations, not logical. Any suggestions on alternative names?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D88707

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll

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