[llvm] a97e97f - [AArch64][GlobalISel] Make <8 x s8> shifts legal and add selection support.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2020-10-01T14:21:18-07:00
New Revision: a97e97faedab0ba57f7c471f778d38cfd18988b8

URL: https://github.com/llvm/llvm-project/commit/a97e97faedab0ba57f7c471f778d38cfd18988b8
DIFF: https://github.com/llvm/llvm-project/commit/a97e97faedab0ba57f7c471f778d38cfd18988b8.diff

LOG: [AArch64][GlobalISel] Make <8 x s8> shifts legal and add selection support.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 1daa2b29b9d5..bb132a33ac5b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -1498,6 +1498,8 @@ bool AArch64InstructionSelector::selectVectorSHL(
     Opc = ImmVal ? AArch64::SHLv8i16_shift : AArch64::USHLv8i16;
   } else if (Ty == LLT::vector(16, 8)) {
     Opc = ImmVal ? AArch64::SHLv16i8_shift : AArch64::USHLv16i8;
+  } else if (Ty == LLT::vector(8, 8)) {
+    Opc = ImmVal ? AArch64::SHLv8i8_shift : AArch64::USHLv8i8;
   } else {
     LLVM_DEBUG(dbgs() << "Unhandled G_SHL type");
     return false;
@@ -1557,6 +1559,9 @@ bool AArch64InstructionSelector::selectVectorAshrLshr(
   } else if (Ty == LLT::vector(16, 8)) {
     Opc = IsASHR ? AArch64::SSHLv16i8 : AArch64::USHLv16i8;
     NegOpc = AArch64::NEGv8i16;
+  } else if (Ty == LLT::vector(8, 8)) {
+    Opc = IsASHR ? AArch64::SSHLv8i8 : AArch64::USHLv8i8;
+    NegOpc = AArch64::NEGv8i8;
   } else {
     LLVM_DEBUG(dbgs() << "Unhandled G_ASHR type");
     return false;

diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 31dde5d76ac7..8e38880034c3 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -124,13 +124,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
           {s32, s32},
           {s32, s64},
           {s64, s64},
+          {v8s8, v8s8},
           {v16s8, v16s8},
           {v4s16, v4s16},
           {v8s16, v8s16},
           {v2s32, v2s32},
           {v4s32, v4s32},
           {v2s64, v2s64},
-
       })
       .clampScalar(1, s32, s64)
       .clampScalar(0, s32, s64)

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
index 8a28012766ef..bf0a95776d5d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
-# R UN: llc -O0 -debugify-and-strip-all-safe -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
+# RUN: llc -O0 -debugify-and-strip-all-safe -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
 ---
 name:            test_shift
 body:             |
@@ -431,3 +431,46 @@ body:             |
     $q0 = COPY %3(<4 x s32>)
     $q1 = COPY %4(<4 x s32>)
 ...
+---
+name: test_shl_v8s8
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_shl_v8s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+    ; CHECK: [[SHL:%[0-9]+]]:_(<8 x s8>) = G_SHL [[COPY]], [[COPY1]](<8 x s8>)
+    ; CHECK: $d0 = COPY [[SHL]](<8 x s8>)
+    %0:_(<8 x s8>) = COPY $d0
+    %1:_(<8 x s8>) = COPY $d1
+    %2:_(<8 x s8>) = G_SHL %0, %1
+    $d0 = COPY %2
+...
+---
+name: test_ashr_v8s8
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_ashr_v8s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+    ; CHECK: [[ASHR:%[0-9]+]]:_(<8 x s8>) = G_ASHR [[COPY]], [[COPY1]](<8 x s8>)
+    ; CHECK: $d0 = COPY [[ASHR]](<8 x s8>)
+    %0:_(<8 x s8>) = COPY $d0
+    %1:_(<8 x s8>) = COPY $d1
+    %2:_(<8 x s8>) = G_ASHR %0, %1
+    $d0 = COPY %2
+...
+
+---
+name: test_lshr_v8s8
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_lshr_v8s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+    ; CHECK: [[LSHR:%[0-9]+]]:_(<8 x s8>) = G_LSHR [[COPY]], [[COPY1]](<8 x s8>)
+    ; CHECK: $d0 = COPY [[LSHR]](<8 x s8>)
+    %0:_(<8 x s8>) = COPY $d0
+    %1:_(<8 x s8>) = COPY $d1
+    %2:_(<8 x s8>) = G_LSHR %0, %1
+    $d0 = COPY %2
+...