[llvm] 66d2e3f - [PowerPC] Add outer product instructions for MMA
Ahsan Saghir via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 16:07:04 PDT 2020
Author: Ahsan Saghir
Date: 2020-09-30T18:06:49-05:00
New Revision: 66d2e3f495948412602db4507359b4612639e523
URL: https://github.com/llvm/llvm-project/commit/66d2e3f495948412602db4507359b4612639e523
DIFF: https://github.com/llvm/llvm-project/commit/66d2e3f495948412602db4507359b4612639e523.diff
LOG: [PowerPC] Add outer product instructions for MMA
This patch adds outer product instructions for MMA, including related infrastructure, and their tests.
Depends on D84968.
Reviewed By: #powerpc, bsaleil, amyk
Differential Revision: https://reviews.llvm.org/D88043
Added:
Modified:
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index a666d28eabf0..5d0f93704fc9 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -528,6 +528,11 @@ struct PPCOperand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()]));
}
+ void addRegVSRpEvenRCOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()]));
+ }
+
void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 38e05414bf01..cc9ffc94ead9 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -212,6 +212,15 @@ static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm,
return MCDisassembler::Success;
}
+static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo & 1)
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
int64_t Address, const void *Decoder) {
// Decode the memri field (imm, reg), which has the low 16-bits as the
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
index d431628adee1..5f0769fd21f9 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -94,6 +94,16 @@ getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
return 0;
}
+unsigned
+PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");
+ unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
+ << 1;
+ return RegBits;
+}
+
unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
index 4504cc6a7405..347e163c9515 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
@@ -93,6 +93,9 @@ class PPCMCCodeEmitter : public MCCodeEmitter {
unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ unsigned getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
/// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 6bdd07f346cb..4ca03298ba88 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -647,6 +647,185 @@ class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
let Inst{31} = 0;
}
+class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<3> AT;
+ bits<6> XA;
+ bits<6> XB;
+
+ let Pattern = pattern;
+
+ let Inst{6-8} = AT;
+ let Inst{9-10} = 0;
+ let Inst{11-15} = XA{4-0};
+ let Inst{16-20} = XB{4-0};
+ let Inst{21-28} = xo;
+ let Inst{29} = XA{5};
+ let Inst{30} = XB{5};
+ let Inst{31} = 0;
+}
+
+class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : PI<1, opcode, OOL, IOL, asmstr, itin> {
+ bits<3> AT;
+ bits<6> XA;
+ bits<6> XB;
+ bits<4> XMSK;
+ bits<4> YMSK;
+ bits<2> PMSK;
+
+ let Pattern = pattern;
+
+ // The prefix.
+ let Inst{6-7} = 3;
+ let Inst{8-11} = 9;
+ let Inst{12-15} = 0;
+ let Inst{16-17} = PMSK;
+ let Inst{18-23} = 0;
+ let Inst{24-27} = XMSK;
+ let Inst{28-31} = YMSK;
+
+ // The instruction.
+ let Inst{38-40} = AT;
+ let Inst{41-42} = 0;
+ let Inst{43-47} = XA{4-0};
+ let Inst{48-52} = XB{4-0};
+ let Inst{53-60} = xo;
+ let Inst{61} = XA{5};
+ let Inst{62} = XB{5};
+ let Inst{63} = 0;
+}
+
+class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : PI<1, opcode, OOL, IOL, asmstr, itin> {
+ bits<3> AT;
+ bits<6> XA;
+ bits<6> XB;
+ bits<4> XMSK;
+ bits<4> YMSK;
+
+ let Pattern = pattern;
+
+ // The prefix.
+ let Inst{6-7} = 3;
+ let Inst{8-11} = 9;
+ let Inst{12-23} = 0;
+ let Inst{24-27} = XMSK;
+ let Inst{28-31} = YMSK;
+
+ // The instruction.
+ let Inst{38-40} = AT;
+ let Inst{41-42} = 0;
+ let Inst{43-47} = XA{4-0};
+ let Inst{48-52} = XB{4-0};
+ let Inst{53-60} = xo;
+ let Inst{61} = XA{5};
+ let Inst{62} = XB{5};
+ let Inst{63} = 0;
+}
+
+class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : PI<1, opcode, OOL, IOL, asmstr, itin> {
+ bits<3> AT;
+ bits<6> XA;
+ bits<6> XB;
+ bits<4> XMSK;
+ bits<2> YMSK;
+
+ let Pattern = pattern;
+
+ // The prefix.
+ let Inst{6-7} = 3;
+ let Inst{8-11} = 9;
+ let Inst{12-23} = 0;
+ let Inst{24-27} = XMSK;
+ let Inst{28-29} = YMSK;
+ let Inst{30-31} = 0;
+
+ // The instruction.
+ let Inst{38-40} = AT;
+ let Inst{41-42} = 0;
+ let Inst{43-47} = XA{4-0};
+ let Inst{48-52} = XB{4-0};
+ let Inst{53-60} = xo;
+ let Inst{61} = XA{5};
+ let Inst{62} = XB{5};
+ let Inst{63} = 0;
+}
+
+class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : PI<1, opcode, OOL, IOL, asmstr, itin> {
+ bits<3> AT;
+ bits<6> XA;
+ bits<6> XB;
+ bits<4> XMSK;
+ bits<4> YMSK;
+ bits<8> PMSK;
+
+ let Pattern = pattern;
+
+ // The prefix.
+ let Inst{6-7} = 3;
+ let Inst{8-11} = 9;
+ let Inst{12-15} = 0;
+ let Inst{16-23} = PMSK;
+ let Inst{24-27} = XMSK;
+ let Inst{28-31} = YMSK;
+
+ // The instruction.
+ let Inst{38-40} = AT;
+ let Inst{41-42} = 0;
+ let Inst{43-47} = XA{4-0};
+ let Inst{48-52} = XB{4-0};
+ let Inst{53-60} = xo;
+ let Inst{61} = XA{5};
+ let Inst{62} = XB{5};
+ let Inst{63} = 0;
+}
+
+class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : PI<1, opcode, OOL, IOL, asmstr, itin> {
+ bits<3> AT;
+ bits<6> XA;
+ bits<6> XB;
+ bits<4> XMSK;
+ bits<4> YMSK;
+ bits<4> PMSK;
+
+ let Pattern = pattern;
+
+ // The prefix.
+ let Inst{6-7} = 3;
+ let Inst{8-11} = 9;
+ let Inst{12-15} = 0;
+ let Inst{16-19} = PMSK;
+ let Inst{20-23} = 0;
+ let Inst{24-27} = XMSK;
+ let Inst{28-31} = YMSK;
+
+ // The instruction.
+ let Inst{38-40} = AT;
+ let Inst{41-42} = 0;
+ let Inst{43-47} = XA{4-0};
+ let Inst{48-52} = XB{4-0};
+ let Inst{53-60} = xo;
+ let Inst{61} = XA{5};
+ let Inst{62} = XB{5};
+ let Inst{63} = 0;
+}
+
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
@@ -802,6 +981,286 @@ let Predicates = [PrefixInstrs] in {
}
}
+// Multiclass definitions for MMA accumulator instructions.
+// ----------------------------------------------------------------------------
+
+// Defines 2 unmasked instructions where the xo field for acc/non-acc version
+// is even/odd.
+multiclass ACC_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
+ string asmstr> {
+ let Predicates = [MMA] in {
+ def NAME :
+ XX3Form_AT3_XAB6<opcode, !or(xo, 0x01), (outs acc:$AT), IOL,
+ !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PP :
+ XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), !con((ins acc:$ATi), IOL),
+ !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+}
+
+// Defines 4 instructions, masked/unmasked with masks 8, 4, 4 bits.
+// The XO field for acc/non-acc version is even/odd.
+multiclass ACC_UM_M844_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
+ string asmstr> {
+ defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
+ let Predicates = [MMA, PrefixInstrs] in {
+ def PM#NAME :
+ MMIRR_XX3Form_XY4P8_XAB6<
+ opcode, !or(xo, 0x01), (outs acc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#PP :
+ MMIRR_XX3Form_XY4P8_XAB6<
+ opcode, xo, (outs acc:$AT),
+ !con((ins acc:$ATi),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+}
+
+// Defines 4 instructions, masked/unmasked with masks 4, 4, 4 bits.
+// The XO field for acc/non-acc version is even/odd.
+multiclass ACC_UM_M444_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
+ string asmstr> {
+ defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
+ let Predicates = [MMA, PrefixInstrs] in {
+ def PM#NAME :
+ MMIRR_XX3Form_XYP4_XAB6<
+ opcode, !or(xo, 0x01), (outs acc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#PP :
+ MMIRR_XX3Form_XYP4_XAB6<
+ opcode, xo, (outs acc:$AT),
+ !con((ins acc:$ATi),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+}
+
+// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits.
+// The XO field for acc/non-acc version is even/odd.
+multiclass ACC_UM_M244_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
+ string asmstr> {
+ defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
+ let Predicates = [MMA, PrefixInstrs] in {
+ def PM#NAME :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, !or(xo, 0x01), (outs acc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#PP :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, xo, (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+}
+
+// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits.
+// Upper nibble of XO field for acc/non-acc version is 0x4/0x6.
+multiclass ACC_UM_M244_XO46<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
+ string asmstr> {
+ let Predicates = [MMA] in {
+ def NAME :
+ XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), IOL,
+ !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PP :
+ XX3Form_AT3_XAB6<
+ opcode, !or(xo, 0x20), (outs acc:$AT), !con((ins acc:$ATi), IOL),
+ !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+ let Predicates = [MMA, PrefixInstrs] in {
+ def PM#NAME :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, xo, (outs acc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#PP :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, !or(xo, 0x20), (outs acc:$AT),
+ !con((ins acc:$ATi),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+}
+
+// Defines 10 instructions, operand negating, unmasked, masked with 2, 4, 4
+// bits. Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
+multiclass ACC_NEG_UM_M244_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
+ string asmbase, string asmstr> {
+ defm NAME : ACC_UM_M244_XOEO<opcode, xo, IOL, asmbase, asmstr>;
+ let Predicates = [MMA] in {
+ def PN : XX3Form_AT3_XAB6<
+ opcode, !or(xo, 0x80), (outs acc:$AT), !con((ins acc:$ATi), IOL),
+ !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def NP : XX3Form_AT3_XAB6<
+ opcode, !or(xo, 0x40), (outs acc:$AT), !con((ins acc:$ATi), IOL),
+ !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def NN : XX3Form_AT3_XAB6<
+ opcode, !or(xo, 0xC0), (outs acc:$AT), !con((ins acc:$ATi), IOL),
+ !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+ let Predicates = [MMA, PrefixInstrs] in {
+ def PM#NAME#PN :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, !or(xo, 0x80), (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#NP :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, !or(xo, 0x40), (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#NN :
+ MMIRR_XX3Form_XY4P2_XAB6<
+ opcode, !or(xo, 0xC0), (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+}
+
+// Defines 5 instructions, unmasked, operand negating.
+// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
+multiclass ACC_NEG_UM_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
+ string asmbase, string asmstr> {
+ defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
+ let Predicates = [MMA] in {
+ def PN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs acc:$AT),
+ !con((ins acc:$ATi), IOL),
+ !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def NP : XX3Form_AT3_XAB6<opcode, !or(xo, 0x40), (outs acc:$AT),
+ !con((ins acc:$ATi), IOL),
+ !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def NN : XX3Form_AT3_XAB6<opcode, !or(xo, 0xC0), (outs acc:$AT),
+ !con((ins acc:$ATi), IOL),
+ !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+}
+
+// Defines 10 instructions, operand negating, unmasked, masked with 4, 4 bits.
+// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
+multiclass ACC_NEG_UM_M44_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
+ string asmbase, string asmstr> {
+ defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>;
+ let Predicates = [MMA, PrefixInstrs] in {
+ def PM#NAME :
+ MMIRR_XX3Form_XY4_XAB6<
+ opcode, !or(xo, 0x01), (outs acc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#PP :
+ MMIRR_XX3Form_XY4_XAB6<
+ opcode, xo, (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#PN :
+ MMIRR_XX3Form_XY4_XAB6<
+ opcode, !or(xo, 0x80), (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
+ !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#NP :
+ MMIRR_XX3Form_XY4_XAB6<
+ opcode, !or(xo, 0x40), (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
+ !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#NN :
+ MMIRR_XX3Form_XY4_XAB6<
+ opcode, !or(xo, 0xC0), (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
+ !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+}
+
+// Defines 10 instructions, operand negating, unmasked, masked with 4, 2 bits.
+// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
+multiclass ACC_NEG_UM_M42_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
+ string asmbase, string asmstr> {
+ defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>;
+ let Predicates = [MMA, PrefixInstrs] in {
+ def PM#NAME :
+ MMIRR_XX3Form_X4Y2_XAB6<
+ opcode, !or(xo, 0x01), (outs acc:$AT),
+ !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#PP :
+ MMIRR_XX3Form_X4Y2_XAB6<
+ opcode, xo, (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#PN :
+ MMIRR_XX3Form_X4Y2_XAB6<
+ opcode, !or(xo, 0x80), (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
+ !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#NP :
+ MMIRR_XX3Form_X4Y2_XAB6<
+ opcode, !or(xo, 0x40), (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
+ !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#NN :
+ MMIRR_XX3Form_X4Y2_XAB6<
+ opcode, !or(xo, 0xC0), (outs acc:$AT),
+ !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
+ !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+}
+
+// End of class definitions.
+//-----------------------------------------------------------------------------
+
let Predicates = [MMA] in {
def XXMFACC :
XForm_AT3<31, 0, 177, (outs acc:$ASo), (ins acc:$AS), "xxmfacc $AS",
@@ -824,8 +1283,62 @@ let Predicates = [MMA] in {
XForm_AT3<31, 3, 177, (outs acc:$AT), (ins), "xxsetaccz $AT",
IIC_VecGeneral, []>;
}
+ def XVI8GER4SPP :
+ XX3Form_AT3_XAB6<59, 99, (outs acc:$AT), (ins acc:$ATi, vsrc:$XA, vsrc:$XB),
+ "xvi8ger4spp $AT, $XA, $XB", IIC_VecGeneral, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+}
+
+let Predicates = [MMA, PrefixInstrs] in {
+ def PMXVI8GER4SPP :
+ MMIRR_XX3Form_XYP4_XAB6<59, 99, (outs acc:$AT),
+ (ins acc:$ATi, vsrc:$XA,vsrc:$XB, u4imm:$XMSK,
+ u4imm:$YMSK, u4imm:$PMSK),
+ "pmxvi8ger4spp $AT, $XA, $XB, $XMSK, $YMSK, $PMSK",
+ IIC_VecGeneral, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
}
+// MMA accumulating/non-accumulating instructions.
+//------------------------------------------------------------------------------
+
+// XVBF16GER2, XVBF16GER2PP, XVBF16GER2PN, XVBF16GER2NP, XVBF16GER2NN
+// PMXVBF16GER2, PMXVBF16GER2PP, PMXVBF16GER2PN, PMXVBF16GER2NP, PMXVBF16GER2NN
+defm XVBF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 50, (ins vsrc:$XA, vsrc:$XB),
+ "xvbf16ger2", "$AT, $XA, $XB">;
+
+// XVI4GER8, XVI4GER8PP, PMXVI4GER8, PMXVI4GER8PP
+defm XVI4GER8 : ACC_UM_M844_XOEO<59, 34, (ins vsrc:$XA, vsrc:$XB),
+ "xvi4ger8", "$AT, $XA, $XB">;
+
+// XVI8GER4, XVI8GER4PP, PMXVI8GER4, PMXVI8GER4PP
+defm XVI8GER4 : ACC_UM_M444_XOEO<59, 2, (ins vsrc:$XA, vsrc:$XB),
+ "xvi8ger4", "$AT, $XA, $XB">;
+
+// XVI16GER2, XVI16GER2PP, PMXVI16GER2, PMXVI16GER2PP
+defm XVI16GER2 : ACC_UM_M244_XO46<59, 75, (ins vsrc:$XA, vsrc:$XB),
+ "xvi16ger2", "$AT, $XA, $XB">;
+
+// XVI16GER2S, XVI16GER2SPP, PMXVI16GER2S, PMXVI16GER2SPP
+defm XVI16GER2S : ACC_UM_M244_XOEO<59, 42, (ins vsrc:$XA, vsrc:$XB),
+ "xvi16ger2s", "$AT, $XA, $XB">;
+
+// XVF16GER2, XVF16GER2PP, XVF16GER2PN, XVF16GER2NP, XVF16GER2NN
+// PMXVF16GER2, PMXVF16GER2PP, PMXVF16GER2PN, PMXVF16GER2NP, PMXVF16GER2NN
+defm XVF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 18, (ins vsrc:$XA, vsrc:$XB),
+ "xvf16ger2", "$AT, $XA, $XB">;
+
+// XVF32GER, XVF32GERPP, XVF32GERPN, XVF32GERNP, XVF32GERPP
+// PMXVF32GER, PMXVF32GERPP, PMXVF32GERPN, PMXVF32GERNP, PMXVF32GERPP
+defm XVF32GER : ACC_NEG_UM_M44_XOM84C<59, 26, (ins vsrc:$XA, vsrc:$XB),
+ "xvf32ger", "$AT, $XA, $XB">;
+
+// XVF64GER, XVF64GERPP, XVF64GERPN, XVF64GERNP, XVF64GERNN
+// PMXVF64GER, PMXVF64GERPP, PMXVF64GERPN, PMXVF64GERNP, PMXVF64GERNN
+defm XVF64GER : ACC_NEG_UM_M42_XOM84C<59, 58, (ins vsrpevenrc:$XA, vsrc:$XB),
+ "xvf64ger", "$AT, $XA, $XB">;
+//------------------------------------------------------------------------------
+
def Concats {
dag VecsToVecPair0 =
(v256i1 (INSERT_SUBREG
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
index e5d7d306b48a..edbeeaf8826d 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -34,6 +34,180 @@
# CHECK: xxsetaccz 0
0x7c 0x03 0x01 0x62
+# CHECK: pmxvf16ger2 0, 1, 2, 4, 4, 2
+0x07 0x90 0x80 0x44 0xec 0x01 0x10 0x98
+
+# CHECK: pmxvf16ger2pp 0, 1, 2, 4, 4, 2
+0x07 0x90 0x80 0x44 0xec 0x01 0x10 0x90
+
+# CHECK: pmxvf16ger2pn 0, 1, 2, 4, 4, 2
+0x07 0x90 0x80 0x44 0xec 0x01 0x14 0x90
+
+# CHECK: pmxvf16ger2np 0, 1, 2, 4, 4, 2
+0x07 0x90 0x80 0x44 0xec 0x01 0x12 0x90
+
+# CHECK: pmxvf16ger2nn 0, 1, 2, 4, 4, 2
+0x07 0x90 0x80 0x44 0xec 0x01 0x16 0x90
+
+# CHECK: pmxvf32ger 0, 1, 2, 4, 4
+0x07 0x90 0x00 0x44 0xec 0x01 0x10 0xd8
+
+# CHECK: pmxvf32gerpp 0, 1, 2, 4, 4
+0x07 0x90 0x00 0x44 0xec 0x01 0x10 0xd0
+
+# CHECK: pmxvf32gerpn 0, 1, 2, 4, 4
+0x07 0x90 0x00 0x44 0xec 0x01 0x14 0xd0
+
+# CHECK: pmxvf32gernp 0, 1, 2, 4, 4
+0x07 0x90 0x00 0x44 0xec 0x01 0x12 0xd0
+
+# CHECK: pmxvf32gernn 0, 1, 2, 4, 4
+0x07 0x90 0x00 0x44 0xec 0x01 0x16 0xd0
+
+# CHECK: pmxvf64ger 0, 0, 2, 4, 3
+0x07 0x90 0x00 0x4c 0xec 0x00 0x11 0xd8
+
+# CHECK: pmxvf64gerpp 0, 2, 2, 4, 3
+0x07 0x90 0x00 0x4c 0xec 0x02 0x11 0xd0
+
+# CHECK: pmxvf64gerpn 0, 4, 2, 4, 3
+0x07 0x90 0x00 0x4c 0xec 0x04 0x15 0xd0
+
+# CHECK: pmxvf64gernp 0, 62, 2, 4, 3
+0x07 0x90 0x00 0x4c 0xec 0x1e 0x13 0xd4
+
+# CHECK: pmxvf64gernn 0, 30, 2, 4, 3
+0x07 0x90 0x00 0x4c 0xec 0x1e 0x17 0xd0
+
+# CHECK: pmxvi4ger8 0, 1, 2, 4, 4, 4
+0x07 0x90 0x04 0x44 0xec 0x01 0x11 0x18
+
+# CHECK: pmxvi4ger8pp 0, 1, 2, 4, 4, 4
+0x07 0x90 0x04 0x44 0xec 0x01 0x11 0x10
+
+# CHECK: pmxvi8ger4 0, 1, 2, 4, 4, 4
+0x07 0x90 0x40 0x44 0xec 0x01 0x10 0x18
+
+# CHECK: pmxvi8ger4pp 0, 1, 2, 4, 4, 4
+0x07 0x90 0x40 0x44 0xec 0x01 0x10 0x10
+
+# CHECK: pmxvi16ger2s 0, 1, 2, 4, 4, 2
+0x07 0x90 0x80 0x44 0xec 0x01 0x11 0x58
+
+# CHECK: pmxvi16ger2spp 0, 1, 2, 4, 4, 2
+0x07 0x90 0x80 0x44 0xec 0x01 0x11 0x50
+
+# CHECK: xvf16ger2 0, 1, 2
+0xec 0x01 0x10 0x98
+
+# CHECK: xvf16ger2pp 0, 1, 2
+0xec 0x01 0x10 0x90
+
+# CHECK: xvf16ger2pn 0, 1, 2
+0xec 0x01 0x14 0x90
+
+# CHECK: xvf16ger2np 0, 1, 2
+0xec 0x01 0x12 0x90
+
+# CHECK: xvf16ger2nn 0, 1, 2
+0xec 0x01 0x16 0x90
+
+# CHECK: xvf32ger 0, 1, 2
+0xec 0x01 0x10 0xd8
+
+# CHECK: xvf32gerpp 0, 1, 2
+0xec 0x01 0x10 0xd0
+
+# CHECK: xvf32gerpn 0, 1, 2
+0xec 0x01 0x14 0xd0
+
+# CHECK: xvf32gernp 0, 1, 2
+0xec 0x01 0x12 0xd0
+
+# CHECK: xvf32gernn 0, 1, 2
+0xec 0x01 0x16 0xd0
+
+# CHECK: xvf64ger 0, 0, 2
+0xec 0x00 0x11 0xd8
+
+# CHECK: xvf64gerpp 0, 2, 2
+0xec 0x02 0x11 0xd0
+
+# CHECK: xvf64gerpn 0, 62, 2
+0xec 0x1e 0x15 0xd4
+
+# CHECK: xvf64gernp 0, 0, 2
+0xec 0x00 0x13 0xd0
+
+# CHECK: xvf64gernn 0, 0, 2
+0xec 0x00 0x17 0xd0
+
+# CHECK: xvi4ger8 0, 1, 2
+0xec 0x01 0x11 0x18
+
+# CHECK: xvi4ger8pp 0, 1, 2
+0xec 0x01 0x11 0x10
+
+# CHECK: xvi8ger4 0, 1, 2
+0xec 0x01 0x10 0x18
+
+# CHECK: xvi8ger4pp 0, 1, 2
+0xec 0x01 0x10 0x10
+
+# CHECK: xvi16ger2s 0, 1, 2
+0xec 0x01 0x11 0x58
+
+# CHECK: xvi16ger2spp 0, 1, 2
+0xec 0x01 0x11 0x50
+
+# CHECK: xvbf16ger2 2, 33, 34
+0xed 0x01 0x11 0x9e
+
+# CHECK: xvbf16ger2pp 1, 33, 34
+0xec 0x81 0x11 0x96
+
+# CHECK: xvbf16ger2pn 2, 33, 34
+0xed 0x01 0x15 0x96
+
+# CHECK: xvbf16ger2np 1, 33, 34
+0xec 0x81 0x13 0x96
+
+# CHECK: xvbf16ger2nn 2, 33, 34
+0xed 0x01 0x17 0x96
+
+# CHECK: pmxvbf16ger2 2, 33, 34, 4, 4, 2
+0x07 0x90 0x80 0x44 0xed 0x01 0x11 0x9e
+
+# CHECK: pmxvbf16ger2pp 1, 33, 34, 4, 4, 2
+0x07 0x90 0x80 0x44 0xec 0x81 0x11 0x96
+
+# CHECK: pmxvbf16ger2pn 2, 33, 34, 4, 4, 2
+0x07 0x90 0x80 0x44 0xed 0x01 0x15 0x96
+
+# CHECK: pmxvbf16ger2np 1, 33, 34, 4, 4, 2
+0x07 0x90 0x80 0x44 0xec 0x81 0x13 0x96
+
+# CHECK: pmxvbf16ger2nn 2, 33, 34, 4, 4, 2
+0x07 0x90 0x80 0x44 0xed 0x01 0x17 0x96
+
+# CHECK: xvi8ger4spp 1, 33, 34
+0xec 0x81 0x13 0x1e
+
+# CHECK: xvi16ger2 1, 33, 34
+0xec 0x81 0x12 0x5e
+
+# CHECK: xvi16ger2pp 1, 33, 34
+0xec 0x81 0x13 0x5e
+
+# CHECK: pmxvi8ger4spp 1, 33, 34, 4, 4, 8
+0x07 0x90 0x80 0x44 0xec 0x81 0x13 0x1e
+
+# CHECK: pmxvi16ger2 1, 33, 34, 4, 4, 2
+0x07 0x90 0x80 0x44 0xec 0x81 0x12 0x5e
+
+# CHECK: pmxvi16ger2pp 1, 33, 34, 4, 4, 2
+0x07 0x90 0x80 0x44 0xec 0x81 0x13 0x5e
+
# CHECK: lxvp 2, 32(4)
0x18 0x44 0x00 0x20
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
index 1abed2d031c2..7ff7e02edafd 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -32,6 +32,238 @@
# CHECK-BE: xxsetaccz 1 # encoding: [0x7c,0x83,0x01,0x62]
# CHECK-LE: xxsetaccz 1 # encoding: [0x62,0x01,0x83,0x7c]
xxsetaccz 1
+# CHECK-BE: pmxvf16ger2 0, 1, 2, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x10,0x98]
+# CHECK-LE: pmxvf16ger2 0, 1, 2, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x98,0x10,0x01,0xec]
+ pmxvf16ger2 0, 1, 2, 4, 4, 2
+# CHECK-BE: pmxvf16ger2pp 0, 1, 2, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x10,0x90]
+# CHECK-LE: pmxvf16ger2pp 0, 1, 2, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x90,0x10,0x01,0xec
+ pmxvf16ger2pp 0, 1, 2, 4, 4, 2
+# CHECK-BE: pmxvf16ger2pn 0, 1, 2, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x14,0x90]
+# CHECK-LE: pmxvf16ger2pn 0, 1, 2, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x90,0x14,0x01,0xec]
+ pmxvf16ger2pn 0, 1, 2, 4, 4, 2
+# CHECK-BE: pmxvf16ger2np 0, 1, 2, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x12,0x90]
+# CHECK-LE: pmxvf16ger2np 0, 1, 2, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x90,0x12,0x01,0xec]
+ pmxvf16ger2np 0, 1, 2, 4, 4, 2
+# CHECK-BE: pmxvf16ger2nn 0, 1, 2, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x16,0x90]
+# CHECK-LE: pmxvf16ger2nn 0, 1, 2, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x90,0x16,0x01,0xec]
+ pmxvf16ger2nn 0, 1, 2, 4, 4, 2
+# CHECK-BE: pmxvf32ger 0, 1, 2, 4, 4 # encoding: [0x07,0x90,0x00,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x10,0xd8]
+# CHECK-LE: pmxvf32ger 0, 1, 2, 4, 4 # encoding: [0x44,0x00,0x90,0x07,
+# CHECK-LE-SAME: 0xd8,0x10,0x01,0xec]
+ pmxvf32ger 0, 1, 2, 4, 4
+# CHECK-BE: pmxvf32gerpp 0, 1, 2, 4, 4 # encoding: [0x07,0x90,0x00,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x10,0xd0]
+# CHECK-LE: pmxvf32gerpp 0, 1, 2, 4, 4 # encoding: [0x44,0x00,0x90,0x07,
+# CHECK-LE-SAME: 0xd0,0x10,0x01,0xec]
+ pmxvf32gerpp 0, 1, 2, 4, 4
+# CHECK-BE: pmxvf32gerpn 0, 1, 2, 4, 4 # encoding: [0x07,0x90,0x00,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x14,0xd0]
+# CHECK-LE: pmxvf32gerpn 0, 1, 2, 4, 4 # encoding: [0x44,0x00,0x90,0x07,
+# CHECK-LE-SAME: 0xd0,0x14,0x01,0xec]
+ pmxvf32gerpn 0, 1, 2, 4, 4
+# CHECK-BE: pmxvf32gernp 0, 1, 2, 4, 4 # encoding: [0x07,0x90,0x00,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x12,0xd0]
+# CHECK-LE: pmxvf32gernp 0, 1, 2, 4, 4 # encoding: [0x44,0x00,0x90,0x07,
+# CHECK-LE-SAME: 0xd0,0x12,0x01,0xec]
+ pmxvf32gernp 0, 1, 2, 4, 4
+# CHECK-BE: pmxvf32gernn 0, 1, 2, 4, 4 # encoding: [0x07,0x90,0x00,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x16,0xd0]
+# CHECK-LE: pmxvf32gernn 0, 1, 2, 4, 4 # encoding: [0x44,0x00,0x90,0x07,
+# CHECK-LE-SAME: 0xd0,0x16,0x01,0xec]
+ pmxvf32gernn 0, 1, 2, 4, 4
+# CHECK-BE: pmxvf64ger 0, 0, 2, 4, 3 # encoding: [0x07,0x90,0x00,0x4c,
+# CHECK-BE-SAME: 0xec,0x00,0x11,0xd8]
+# CHECK-LE: pmxvf64ger 0, 0, 2, 4, 3 # encoding: [0x4c,0x00,0x90,0x07,
+# CHECK-LE-SAME: 0xd8,0x11,0x00,0xec]
+ pmxvf64ger 0, 0, 2, 4, 3
+# CHECK-BE: pmxvf64gerpp 0, 2, 2, 4, 3 # encoding: [0x07,0x90,0x00,0x4c,
+# CHECK-BE-SAME: 0xec,0x02,0x11,0xd0]
+# CHECK-LE: pmxvf64gerpp 0, 2, 2, 4, 3 # encoding: [0x4c,0x00,0x90,0x07,
+# CHECK-LE-SAME: 0xd0,0x11,0x02,0xec]
+ pmxvf64gerpp 0, 2, 2, 4, 3
+# CHECK-BE: pmxvf64gerpn 0, 4, 2, 4, 3 # encoding: [0x07,0x90,0x00,0x4c,
+# CHECK-BE-SAME: 0xec,0x04,0x15,0xd0]
+# CHECK-LE: pmxvf64gerpn 0, 4, 2, 4, 3 # encoding: [0x4c,0x00,0x90,0x07,
+# CHECK-LE-SAME: 0xd0,0x15,0x04,0xec]
+ pmxvf64gerpn 0, 4, 2, 4, 3
+# CHECK-BE: pmxvf64gernp 0, 32, 2, 4, 3 # encoding: [0x07,0x90,0x00,0x4c,
+# CHECK-BE-SAME: 0xec,0x00,0x13,0xd4]
+# CHECK-LE: pmxvf64gernp 0, 32, 2, 4, 3 # encoding: [0x4c,0x00,0x90,0x07,
+# CHECK-LE-SAME: 0xd4,0x13,0x00,0xec]
+ pmxvf64gernp 0, 32, 2, 4, 3
+# CHECK-BE: pmxvf64gernn 0, 62, 2, 4, 3 # encoding: [0x07,0x90,0x00,0x4c,
+# CHECK-BE-SAME: 0xec,0x1e,0x17,0xd4]
+# CHECK-LE: pmxvf64gernn 0, 62, 2, 4, 3 # encoding: [0x4c,0x00,0x90,0x07,
+# CHECK-LE-SAME: 0xd4,0x17,0x1e,0xec]
+ pmxvf64gernn 0, 62, 2, 4, 3
+# CHECK-BE: pmxvi4ger8 0, 1, 2, 4, 4, 4 # encoding: [0x07,0x90,0x04,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x11,0x18]
+# CHECK-LE: pmxvi4ger8 0, 1, 2, 4, 4, 4 # encoding: [0x44,0x04,0x90,0x07
+# CHECK-LE-SAME: 0x18,0x11,0x01,0xec]
+ pmxvi4ger8 0, 1, 2, 4, 4, 4
+# CHECK-BE: pmxvi4ger8pp 0, 1, 2, 4, 4, 4 # encoding: [0x07,0x90,0x04,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x11,0x10]
+# CHECK-LE: pmxvi4ger8pp 0, 1, 2, 4, 4, 4 # encoding: [0x44,0x04,0x90,0x07
+# CHECK-LE-SAME: 0x10,0x11,0x01,0xec]
+ pmxvi4ger8pp 0, 1, 2, 4, 4, 4
+# CHECK-BE: pmxvi8ger4 0, 1, 2, 4, 4, 4 # encoding: [0x07,0x90,0x40,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x10,0x18]
+# CHECK-LE: pmxvi8ger4 0, 1, 2, 4, 4, 4 # encoding: [0x44,0x40,0x90,0x07,
+# CHECK-LE-SAME: 0x18,0x10,0x01,0xec]
+ pmxvi8ger4 0, 1, 2, 4, 4, 4
+# CHECK-BE: pmxvi8ger4pp 0, 1, 2, 4, 4, 4 # encoding: [0x07,0x90,0x40,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x10,0x10]
+# CHECK-LE: pmxvi8ger4pp 0, 1, 2, 4, 4, 4 # encoding: [0x44,0x40,0x90,0x07,
+# CHECK-LE-SAME: 0x10,0x10,0x01,0xec]
+ pmxvi8ger4pp 0, 1, 2, 4, 4, 4
+# CHECK-BE: pmxvi16ger2s 0, 1, 2, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x11,0x58]
+# CHECK-LE: pmxvi16ger2s 0, 1, 2, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x58,0x11,0x01,0xec]
+ pmxvi16ger2s 0, 1, 2, 4, 4, 2
+# CHECK-BE: pmxvi16ger2spp 0, 1, 2, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x01,0x11,0x50]
+# CHECK-LE: pmxvi16ger2spp 0, 1, 2, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x50,0x11,0x01,0xec]
+ pmxvi16ger2spp 0, 1, 2, 4, 4, 2
+# CHECK-BE: xvf16ger2 0, 1, 2 # encoding: [0xec,0x01,0x10,0x98]
+# CHECK-LE: xvf16ger2 0, 1, 2 # encoding: [0x98,0x10,0x01,0xec]
+ xvf16ger2 0, 1, 2
+# CHECK-BE: xvf16ger2pp 0, 1, 2 # encoding: [0xec,0x01,0x10,0x90]
+# CHECK-LE: xvf16ger2pp 0, 1, 2 # encoding: [0x90,0x10,0x01,0xec]
+ xvf16ger2pp 0, 1, 2
+# CHECK-BE: xvf16ger2pn 0, 1, 2 # encoding: [0xec,0x01,0x14,0x90]
+# CHECK-LE: xvf16ger2pn 0, 1, 2 # encoding: [0x90,0x14,0x01,0xec]
+ xvf16ger2pn 0, 1, 2
+# CHECK-BE: xvf16ger2np 0, 1, 2 # encoding: [0xec,0x01,0x12,0x90]
+# CHECK-LE: xvf16ger2np 0, 1, 2 # encoding: [0x90,0x12,0x01,0xec]
+ xvf16ger2np 0, 1, 2
+# CHECK-BE: xvf16ger2nn 0, 1, 2 # encoding: [0xec,0x01,0x16,0x90]
+# CHECK-LE: xvf16ger2nn 0, 1, 2 # encoding: [0x90,0x16,0x01,0xec]
+ xvf16ger2nn 0, 1, 2
+# CHECK-BE: xvf32ger 0, 1, 2 # encoding: [0xec,0x01,0x10,0xd8]
+# CHECK-LE: xvf32ger 0, 1, 2 # encoding: [0xd8,0x10,0x01,0xec]
+ xvf32ger 0, 1, 2
+# CHECK-BE: xvf32gerpp 0, 1, 2 # encoding: [0xec,0x01,0x10,0xd0]
+# CHECK-LE: xvf32gerpp 0, 1, 2 # encoding: [0xd0,0x10,0x01,0xec]
+ xvf32gerpp 0, 1, 2
+# CHECK-BE: xvf32gerpn 0, 1, 2 # encoding: [0xec,0x01,0x14,0xd0]
+# CHECK-LE: xvf32gerpn 0, 1, 2 # encoding: [0xd0,0x14,0x01,0xec]
+ xvf32gerpn 0, 1, 2
+# CHECK-BE: xvf32gernp 0, 1, 2 # encoding: [0xec,0x01,0x12,0xd0]
+# CHECK-LE: xvf32gernp 0, 1, 2 # encoding: [0xd0,0x12,0x01,0xec]
+ xvf32gernp 0, 1, 2
+# CHECK-BE: xvf32gernn 0, 1, 2 # encoding: [0xec,0x01,0x16,0xd0]
+# CHECK-LE: xvf32gernn 0, 1, 2 # encoding: [0xd0,0x16,0x01,0xec]
+ xvf32gernn 0, 1, 2
+# CHECK-BE: xvf64ger 0, 2, 2 # encoding: [0xec,0x02,0x11,0xd8]
+# CHECK-LE: xvf64ger 0, 2, 2 # encoding: [0xd8,0x11,0x02,0xec]
+ xvf64ger 0, 2, 2
+# CHECK-BE: xvf64gerpp 0, 0, 2 # encoding: [0xec,0x00,0x11,0xd0]
+# CHECK-LE: xvf64gerpp 0, 0, 2 # encoding: [0xd0,0x11,0x00,0xec]
+ xvf64gerpp 0, 0, 2
+# CHECK-BE: xvf64gerpn 0, 4, 2 # encoding: [0xec,0x04,0x15,0xd0]
+# CHECK-LE: xvf64gerpn 0, 4, 2 # encoding: [0xd0,0x15,0x04,0xec]
+ xvf64gerpn 0, 4, 2
+# CHECK-BE: xvf64gernp 0, 62, 2 # encoding: [0xec,0x1e,0x13,0xd4]
+# CHECK-LE: xvf64gernp 0, 62, 2 # encoding: [0xd4,0x13,0x1e,0xec]
+ xvf64gernp 0, 62, 2
+# CHECK-BE: xvf64gernn 0, 0, 2 # encoding: [0xec,0x00,0x17,0xd0]
+# CHECK-LE: xvf64gernn 0, 0, 2 # encoding: [0xd0,0x17,0x00,0xec]
+ xvf64gernn 0, 0, 2
+# CHECK-BE: xvi4ger8 0, 1, 2 # encoding: [0xec,0x01,0x11,0x18]
+# CHECK-LE: xvi4ger8 0, 1, 2 # encoding: [0x18,0x11,0x01,0xec]
+ xvi4ger8 0, 1, 2
+# CHECK-BE: xvi4ger8pp 0, 1, 2 # encoding: [0xec,0x01,0x11,0x10]
+# CHECK-LE: xvi4ger8pp 0, 1, 2 # encoding: [0x10,0x11,0x01,0xec]
+ xvi4ger8pp 0, 1, 2
+# CHECK-BE: xvi8ger4 0, 1, 2 # encoding: [0xec,0x01,0x10,0x18]
+# CHECK-LE: xvi8ger4 0, 1, 2 # encoding: [0x18,0x10,0x01,0xec]
+ xvi8ger4 0, 1, 2
+# CHECK-BE: xvi8ger4pp 0, 1, 2 # encoding: [0xec,0x01,0x10,0x10]
+# CHECK-LE: xvi8ger4pp 0, 1, 2 # encoding: [0x10,0x10,0x01,0xec]
+ xvi8ger4pp 0, 1, 2
+# CHECK-BE: xvi16ger2s 0, 1, 2 # encoding: [0xec,0x01,0x11,0x58]
+# CHECK-LE: xvi16ger2s 0, 1, 2 # encoding: [0x58,0x11,0x01,0xec]
+ xvi16ger2s 0, 1, 2
+# CHECK-BE: xvi16ger2spp 0, 1, 2 # encoding: [0xec,0x01,0x11,0x50]
+# CHECK-LE: xvi16ger2spp 0, 1, 2 # encoding: [0x50,0x11,0x01,0xec]
+ xvi16ger2spp 0, 1, 2
+# CHECK-BE: xvbf16ger2 2, 33, 34 # encoding: [0xed,0x01,0x11,0x9e]
+# CHECK-LE: xvbf16ger2 2, 33, 34 # encoding: [0x9e,0x11,0x01,0xed]
+ xvbf16ger2 2, 33, 34
+# CHECK-BE: xvbf16ger2pp 1, 33, 34 # encoding: [0xec,0x81,0x11,0x96]
+# CHECK-LE: xvbf16ger2pp 1, 33, 34 # encoding: [0x96,0x11,0x81,0xec]
+ xvbf16ger2pp 1, 33, 34
+# CHECK-BE: xvbf16ger2pn 2, 33, 34 # encoding: [0xed,0x01,0x15,0x96]
+# CHECK-LE: xvbf16ger2pn 2, 33, 34 # encoding: [0x96,0x15,0x01,0xed]
+ xvbf16ger2pn 2, 33, 34
+# CHECK-BE: xvbf16ger2np 1, 33, 34 # encoding: [0xec,0x81,0x13,0x96]
+# CHECK-LE: xvbf16ger2np 1, 33, 34 # encoding: [0x96,0x13,0x81,0xec]
+ xvbf16ger2np 1, 33, 34
+# CHECK-BE: xvbf16ger2nn 2, 33, 34 # encoding: [0xed,0x01,0x17,0x96]
+# CHECK-LE: xvbf16ger2nn 2, 33, 34 # encoding: [0x96,0x17,0x01,0xed]
+ xvbf16ger2nn 2, 33, 34
+# CHECK-BE: pmxvbf16ger2 2, 33, 34, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xed,0x01,0x11,0x9e]
+# CHECK-LE: pmxvbf16ger2 2, 33, 34, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x9e,0x11,0x01,0xed]
+ pmxvbf16ger2 2, 33, 34, 4, 4, 2
+# CHECK-BE: pmxvbf16ger2pp 1, 33, 34, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x81,0x11,0x96]
+# CHECK-LE: pmxvbf16ger2pp 1, 33, 34, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x96,0x11,0x81,0xec]
+ pmxvbf16ger2pp 1, 33, 34, 4, 4, 2
+# CHECK-BE: pmxvbf16ger2pn 2, 33, 34, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xed,0x01,0x15,0x96]
+# CHECK-LE: pmxvbf16ger2pn 2, 33, 34, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x96,0x15,0x01,0xed]
+ pmxvbf16ger2pn 2, 33, 34, 4, 4, 2
+# CHECK-BE: pmxvbf16ger2np 1, 33, 34, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x81,0x13,0x96]
+# CHECK-LE: pmxvbf16ger2np 1, 33, 34, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x96,0x13,0x81,0xec]
+ pmxvbf16ger2np 1, 33, 34, 4, 4, 2
+# CHECK-BE: pmxvbf16ger2nn 2, 33, 34, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xed,0x01,0x17,0x96]
+# CHECK-LE: pmxvbf16ger2nn 2, 33, 34, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x96,0x17,0x01,0xed]
+ pmxvbf16ger2nn 2, 33, 34, 4, 4, 2
+# CHECK-BE: xvi8ger4spp 1, 33, 34 # encoding: [0xec,0x81,0x13,0x1e]
+# CHECK-LE: xvi8ger4spp 1, 33, 34 # encoding: [0x1e,0x13,0x81,0xec]
+ xvi8ger4spp 1, 33, 34
+# CHECK-BE: xvi16ger2 1, 33, 34 # encoding: [0xec,0x81,0x12,0x5e]
+# CHECK-LE: xvi16ger2 1, 33, 34 # encoding: [0x5e,0x12,0x81,0xec]
+ xvi16ger2 1, 33, 34
+# CHECK-BE: xvi16ger2pp 1, 33, 34 # encoding: [0xec,0x81,0x13,0x5e]
+# CHECK-LE: xvi16ger2pp 1, 33, 34 # encoding: [0x5e,0x13,0x81,0xec]
+ xvi16ger2pp 1, 33, 34
+# CHECK-BE: pmxvi8ger4spp 1, 33, 34, 4, 4, 8 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x81,0x13,0x1e]
+# CHECK-LE: pmxvi8ger4spp 1, 33, 34, 4, 4, 8 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x1e,0x13,0x81,0xec]
+ pmxvi8ger4spp 1, 33, 34, 4, 4, 8
+# CHECK-BE: pmxvi16ger2 1, 33, 34, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x81,0x12,0x5e]
+# CHECK-LE: pmxvi16ger2 1, 33, 34, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x5e,0x12,0x81,0xec]
+ pmxvi16ger2 1, 33, 34, 4, 4, 2
+# CHECK-BE: pmxvi16ger2pp 1, 33, 34, 4, 4, 2 # encoding: [0x07,0x90,0x80,0x44,
+# CHECK-BE-SAME: 0xec,0x81,0x13,0x5e]
+# CHECK-LE: pmxvi16ger2pp 1, 33, 34, 4, 4, 2 # encoding: [0x44,0x80,0x90,0x07,
+# CHECK-LE-SAME: 0x5e,0x13,0x81,0xec]
+ pmxvi16ger2pp 1, 33, 34, 4, 4, 2
# CHECK-BE: lxvp 2, 32(4) # encoding: [0x18,0x44,0x00,0x20]
# CHECK-LE: lxvp 2, 32(4) # encoding: [0x20,0x00,0x44,0x18]
lxvp 2, 32(4)
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